Publication 2006 Issue No. 3 - March Abstract - Processor Array Architectures for Deep Packet Classification
Processor Array Architectures for Deep Packet Classification
March 2006 (vol. 17 no. 3)
pp. 241-252
 ASCII Text x Fayez Gebali, A.N.M. Ehtesham Rafiq, "Processor Array Architectures for Deep Packet Classification," IEEE Transactions on Parallel and Distributed Systems, vol. 17, no. 3, pp. 241-252, March, 2006.
 BibTex x @article{ 10.1109/TPDS.2006.39,author = {Fayez Gebali and A.N.M. Ehtesham Rafiq},title = {Processor Array Architectures for Deep Packet Classification},journal ={IEEE Transactions on Parallel and Distributed Systems},volume = {17},number = {3},issn = {1045-9219},year = {2006},pages = {241-252},doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2006.39},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on Parallel and Distributed SystemsTI - Processor Array Architectures for Deep Packet ClassificationIS - 3SN - 1045-9219SP241EP252EPD - 241-252A1 - Fayez Gebali, A1 - A.N.M. Ehtesham Rafiq, PY - 2006KW - Processor arrayKW - string searchKW - deep packet classificationKW - parallel hardware.VL - 17JA - IEEE Transactions on Parallel and Distributed SystemsER -
Fayez Gebali, IEEE Computer Society

Abstract—This paper presents a systematic technique for expressing a string search algorithm as a regular iterative expression to explore all possible processor arrays for deep packet classification. The computation domain of the algorithm is obtained and three affine scheduling functions are presented. The technique allows some of the algorithm variables to be pipelined while others are broadcast over system-wide buses. Nine possible processor array structures are obtained and analyzed in terms of speed, area, power, and I/O timing requirements. Time complexities are derived analytically and through extensive numerical simulations. The proposed designs exhibit optimum speed and area complexities. The processor arrays are compared with previously derived processor arrays for the string matching problem.

[1] A.N.M.E. Rafiq, M.W. El-Kharashi, and F. Gebali, “A Fast String Search Algorithm for Deep Packet Classification,” Computer Comm., vol. 27, no. 15, pp. 1524-1538, Sept. 2004.
[2] H.T. Kung and C.E. Leiserson, “Systolic Arrays for VLSI,” Proc. Sparse Matrix Symp., pp. 256-282, 1978.
[3] S.K. Rao and T. Kailath, “Regular Iterative Algorithms and Their Implementation on Processor Arrays,” Proc. IEEE, vol. 76, no. 3, pp. 259-269, Mar. 1988.
[4] S.Y. Kung, VLSI Array Processors. Englewood Cliffs, N.J.: Prentice-Hall, 1988.
[5] E.M. M. Abdel-Raheem, “Design and VLSI Implementation of Multirate Filter Banks,” PhD dissertation, Dept. of Electrical and Computer Eng., Univ. of Victoria, 1995.
[6] E. Abdel-Raheem, F. El-Guibaly, and A. Antoniou, “Systolic Implementation of FIR Decimators and Interpolators,” IEE Proc. Circuits Device System, vol. 141, pp. 489-492, Dec. 1994.
[7] M.O. Esonu, A.J. Alkhalili, S. Hariri, and D. Al-Khalili, “Systolic Arrays— How to Choose Them,” IEE Proc.-E Computers and Digital Techniques, vol. 139, no. 3, pp. 179-188, May 1992.
[8] J.M. D. Y. Wong, “Optimization of Computation Time for Systolic Arrays,” IEEE Trans. Computers, vol. 41, no. 2, pp. 159-177, Feb. 1992.
[9] F. El-Guibaly and A. Tawfik, “Mapping 3D IIR Digital Filter onto Systolic Arrays,” Multidimensional Systems and Signal Processing, vol. 7, no. 1, pp. 7-26, Jan. 1996.
[10] M. Nossik, “Optimizing Network Processing with Deep Packet Classification,” OPTIMIZING_WP.pdf, http://www.idt.comdocs/, 2002.
[11] S. Iyer, R.R. Kompella, and A. Shelat, “ClassiPI: An Architecture for Fast and Flexible Packet Classification,” IEEE Network, vol. 15, no. 2, pp. 33-41, Mar./Apr. 2001.
[12] D. Bursky, “Search Engines Take on Larger Forwarding Tables,” Electronic Design, vol. 51, no. 27, p. 48, 2003.
[13] M. Peyravian, G. Davis, and J. Calvignac, “Search Engine Implications for Network Processor,” IEEE Network, vol. 17, no. 4, pp. 12-14, July/Aug. 2003.
[14] G.A. Stephen, String Searching Algorithms, Lecture Notes Series on Computing, D.T. Lee, ed., Bangor, Gwynedd, UK: World Scientific, vol. 3, 1994.
[15] T. Lecroq, “Experiments on String Matching in Memory Structures,” Software: Practice and Experience, vol. 28, no. 5, pp. 561-568, Apr. 1998.
[16] J. Jájá, An Introduction to Parallel Algorithms, Reading, Mass.: Addison-Wesley, ch. 7, pp. 311-365, 1992.
[17] M. Crochemore, Z. Galil, L. Gasieniec, K. Park, and W. Rytter, “Constant-Time Randomized Parallel String Matching,” SIAM J. Computing, vol. 26, no. 4, pp. 950-960, Aug. 1997.
[18] U.Z. T. Goldberg, “Faster Parallel String-Matching via Larger Deterministic Samples,” J. Algorithms, vol. 16, no. 2, pp. 295-308, Mar. 1994.
[19] Z. Galil, “A Constant-Time Optimal Parallel String-Matching Algorithm,” J. Assoc. for Computing Machinery, vol. 42, no. 4, pp. 908-918, July 1995.
[20] J. Misra, “Derivation of a Parallel String Matching Algorithm,” Information Processing Letters, vol. 85, no. 5, pp. 255-260, Mar. 2003.
[21] J. Misra, “Powerlist: A Structure for Parallel Recursion,” ACM Trans. Programming Languages and Systems, vol. 16, no. 6, pp. 1737-1767, Nov. 1994.
[22] K.L. Chung, “${\cal{O}}(1){\hbox{-}}{\rm{Time}}$ Parallel String-Matching Algorithm with VLDCs,” Pattern Recognition Letters, vol. 17, no. 5, pp. 475-479, May 1996.
[23] A.A. Bertossi and F. Logi, “Parallel String-Matching with Variable-Length Don't Cares,” J. Parallel and Distributed Computing, vol. 22, no. 2, pp. 229-234, Aug. 1994.
[24] Y. Takefuji, T. Tanaka, and K.C. Lee, “A Parallel String Search Algorithm,” IEEE Trans. Systems, Man, and Cybernetics, vol. 22, no. 2, pp. 332-336, Mar./Apr. 1992.
[25] H.D. Cheng and K.S. Fu, “VLSI Architectures for String Matching and Pattern Matching,” Pattern Recognition, vol. 20, no. 1, pp. 125-141, 1987.
[26] M.E. Isenman and D.E. Shasha, “Performance and Architectural Issues for String Matching,” IEEE Trans. Computers, vol. 39, no. 2, pp. 238-250, Feb. 1990.
[27] A.V. Aho and J.D. Ulman, Principles of Compiler Design, Reading, Mass.: Addison-Wesley, pp. 91-94, 1977.
[28] M.J. Foster and H.T. Kung, “The Design of Special-Purpose VLSI Chips: Example and Opinions,” Proc. Seventh Ann. Symp. Computer Architecture, Int'l Conf. Computer Architecture, pp. 300-307, May 1980.
[29] A. Mukherjee, “Hardware Algorithms for Determining Similarity between Two Strings,” IEEE Trans. Computers, vol. 38, no. 4, pp. 600-603, Apr. 1989.
[30] J.H. Park and K.M. George, “Efficient Parallel Hardware Algorithms for String Matching,” Microprocessors and Microsystems, vol. 23, no. 3, pp. 155-168, Oct. 1999.
[31] P.D. Michailidis and K.G. Margaritis, “Parallel Architecture for Flexible Approximate Text Searching,” CD-ROM Proc. Seventh WSEAS Int'l Multiconf. Circuits, Systems, Comm. and Computers (WSEAS-CSCC 2003), July 2003.
[32] P.D. Michailidis and K.G. Margaritis, “Bit-Level Processor Array Architecture for Flexible String Matching,” Proc. First Balkan Conf. Informatics (BCI 2003), pp. 517-526, Nov. 2003.
[33] K.R.R. Sastry and N. Ranganathan, “CASM— A VLSI Chip for Approximate String-Matching,” IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 17, no. 8, pp. 824-830, Aug. 1995.
[34] P.R. Panda, N.D. Dutt, and A. Nicolau, “On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-Based Systems,” ACM Trans. Design Automation of Electronic Systems, vol. 5, no. 3, pp. 682-704, July 2000.
[35] F. Elguibaly, “A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 902-908, 2000.
[36] F. Elguibaly, “Merged Inner-Prodcut Processor Using the Modified Booth Algorithm,” Canadian J. Electrical and Computer Eng., vol. 25, no. 4, pp. 133-139, 2000.
[37] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Addison-Wesley, 1992.

Index Terms:
Processor array, string search, deep packet classification, parallel hardware.
Citation:
Fayez Gebali, A.N.M. Ehtesham Rafiq, "Processor Array Architectures for Deep Packet Classification," IEEE Transactions on Parallel and Distributed Systems, vol. 17, no. 3, pp. 241-252, March 2006, doi:10.1109/TPDS.2006.39