This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
February 2005 (vol. 16 no. 2)
pp. 113-129
ASCII Text
x 
 
Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli, "NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip," IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, February, 2005.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2005.22,
author = {Davide Bertozzi and Antoine Jalabert and Srinivasan Murali and Rutuparna Tamhankar and Stergios Stergiou and Luca Benini and Giovanni De Micheli},
title = {NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {16},
number = {2},
issn = {1045-9219},
year = {2005},
pages = {113-129},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2005.22},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IS - 2
SN - 1045-9219
SP113
EP129
EPD - 113-129
A1 - Davide Bertozzi,
A1 - Antoine Jalabert,
A1 - Srinivasan Murali,
A1 - Rutuparna Tamhankar,
A1 - Stergios Stergiou,
A1 - Luca Benini,
A1 - Giovanni De Micheli,
PY - 2005
KW - Systems-on-chip
KW - networks on chip
KW - synthesis
KW - mapping
KW - architecture.
VL - 16
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 

Abstract—The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of Network-on-Chip (NoC) architectures that have been proposed recently for System-on-Chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This paper illustrates a complete synthesis flow, called NetChip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, \timespipesCompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called \timespipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented in the paper, showing the powerful design space exploration capabilities of the proposed methodology and tools.

[1] M. Sgroi et al., “Addressing the System-on-a-Chip Interconnect Woes through Communication-Based Design,” Proc. Design Automation Conf., pp. 667-672, 2001.
[2] L. Benini and G. De Micheli, “Networks on Chips: A New SoC Paradigm,” Computer, pp. 70-78, Jan. 2002.
[3] P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet Switched Interconnections,” Proc. DATE 2000, pp. 250-256, Mar. 2000.
[4] F. Boekhorst, “Ambient Intelligence, the Next Paradigm for Consumer Electronics: How Will it Affect Silicon,” Proc. Int'l Solid State Circuits Conf. 2002, pp. 28-31, Feb. 2002.
[5] S. Kumar et al., “A Network on Chip Architecture and Design Methodology,” Proc. Int'l Symp. VLSI 2002, pp. 105-112, Apr. 2002.
[6] D. Bertozzi, L. Benini, and G. De Micheli, “Low Power Error Resilient Encoding for On-Chip Data Buses,” Proc. Conf. Design Automation and Testing in Europe DATE 2002, pp. 102-109, Mar. 2002.
[7] E. Rijpkema et al., “Trade-Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip,” Proc. Conf. DATE 2003, pp. 350-355, Mar. 2003.
[8] F. Karim et al., “On-Chip Communication Architecture for OC-768 Network Processors,” Proc. Design Automation Conf., pp. 678-678, June 2001.
[9] K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli, “System Level Design: Orthogonalization of Concerns and Platform-Based Design,” IEEE Trans. Computer-Aided Design of Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
[10] H. Zhang et al., “A 1V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing,” IEEE J. Solid State Circuits, vol. 35, no. 11, pp. 1697-1704, Nov. 2000.
[11] X. Zhu and S. Malik, ”A Hierarchical Modeling Framework for On-Chip Communication Architectures,” Proc. Int'l Conf. Computer Design 2002, pp. 663-671, Nov. 2002.
[12] I. Saastamoinen, D. Siguenza-Tortosa, and J. Nurmi, “Interconnect IP Node for Future System-on-Chip Designs,” Proc. First IEEE Int'l Workshop Electronic Design, Test and Applications, pp. 116-120, Jan. 2002.
[13] S.J. Lee et al., “An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip,” Digest of Technical Papers, ISSCC 2003, pp. 468-469, Feb. 2003.
[14] A. Jantsch and H. Tenhunen, Networks on Chip. Kluwer Academic Publishers, 2003.
[15] S.J. Krolikoski et al., “Methodology and Technology for Virtual Component Driven Hardware/Software Co-Design on the System-Level,” Proc. IEEE Int'l Symp. Circuits and Systems '99, pp. 456-459, June 1999.
[16] E.B. Van der Tol and E.G.T. Jaspers, “Mapping of MPEG-4 Decoding on a Flexible Architecture Platform,” Proc. SPIE 2002, pp. 1-13, Jan. 2002.
[17] E.G.T. Jaspers et al., “Chip-set for Video Display of Multimedia Information,” IEEE Trans. Consumer Electronics, vol 45, no. 3, pp. 707-716, Aug. 1999.
[18] A. Pinto et al., “Efficient Synthesis of Networks on Chip,” Proc. Int'l Conf. Computer Design 2003, pp. 146-150, Oct. 2003.
[19] D. Whelihan and H. Schmit, “Memory Optimization in Single Chip Network Fabrics,” Proc. Design Automation Conf. 2002, pp. 530-535, June 2002.
[20] W.H. Ho and T.M. Pinkston, “A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns,” Proc. Symp. High Performance Computer Architecture 2003, pp. 377-388, Feb. 2003.
[21] P. Wielage and K. Goossens, “Networks on Silicon: Blessing or Nightmare?” Proc. Euromicro Symp. Digital System Design DSD 2002, pp. 196-200, Sept. 2002.
[22] J. Hu and R. Marculescu, “Energy-Aware Mapping for Tile-Based NOC Architectures under Performance Constraints,” Proc. Asia and South Pacific Design Automation Conf. 2003, pp. 233-239, Jan. 2003.
[23] J. Hu and R. Marculescu, “Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures,” Proc. DATE Conf. 2003, Mar. 2003.
[24] M. Dallosso et al., “$\times$ Pipes: A Latency Insensitive Parameterized Network-on-chip Architecture for Multi-Processor SoCs,” pp. 536-539, Proc. Int'l Conf. Computer Design, 2003.
[25] A. Jalabert et al., “$\times$ pipesCompiler: A Tool For Instantiating Application Specific Networks on Chips,” Proc. Conf. DATE, 2004.
[26] S. Murali and G. De Micheli, “Bandwidth Constrained Mapping of Cores onto NoC Architectures,” Proc. Conf. DATE, 2004.
[27] S. Murali and G. De Micheli, “SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs,” Proc. Design Automation Conf., 2004.
[28] J.G. Kim and Y.D. Kim, “A Linear Programming-Based Algorithm for Floorplanning in VLSI Design,” IEEE Trans. CAD, pp. 584-592, vol. 22, no. 5 , May 2003.
[29] M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. W.H. Freeman, 1979.
[30] D. Culler, J.P. Singh, and A. Gupta, Parallel Computer Architecture, a Hardware/Software Approach. Morgan Kaufmann, 1999.
[31] K. Compton and S. Hauck, “Reconfigurable Computing: a Survey of System and Software,” ACM Computing Surveys, pp. 171-210, vol. 34, no. 2, June 2002.
[32] R. Tessier and W. Burleson, “Reconfigurable Computing and Digital Signal Processing: A Survey,” J. VLSI Signal Processing, pp. 7-27, vol. 28, no. 3, May 2001.
[33] N. Sherwani, Algorithms for VLSI Physical Design Automation, pp. 187-189. Kluwer Academic Publishers, 1995.
[34] W.J. Dally and B. Towles, “Route Packets, not Wires: On-Chip Interconnection Networks,” Proc. Design and Automation Conf. DAC 2001, pp. 684-689, June 2001.
[35] W.J. Dally and S. Lacy, “VLSI Architecture: Past, Present and Future,” Proc. Conf. Advanced Research in VLSI, pp. 232-241, 1999.
[36] D. Wingard, “MicroNetwork-Based Integration for SoCs,” Proc. Design Automation Conf. DAC 2001, pp. 673-677, June 2001.
[37] H.S Wang et al., “Orion: A Power-Performance Simulator for Interconnection Networks,” IEEE MICRO, Nov. 2002.
[38] R. Ho, K. Mai, and M. Horowitz, “The Future of Wires,” Proc. IEEE, pp. 490-504, Apr. 2001.
[39] D. Wiklund and D. Liu, “SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems,” Proc. Int'l Parallel and Distributed Processing Symp. 2003, pp. 78-85, 2003.
[40] L.P. Carloni, K.L. McMillan, and A.L. Sangiovanni Vincentelli, “Theory of Latency-Insensitive Design,” IEEE Trans. CAD of ICs and Systems, vol. 20, no. 9, pp. 1059-1076, Sept. 2001.
[41] L. Scheffer, “Methodologies and Tools for Pipelined On-Chip Interconnects,” Proc. Int'l Conf. Computer Design, pp. 152-157, 2002.
[42] Tensilica Offload Engine, http://www.tensilica.com/htmlpr_2003_05_12.html , 2004.
[43] VSI Alliance, http:/www.vsi.org/, 2004.
[44] Open Core Protocol, http:/www.ocpip.org/, 2004.

Index Terms:
Systems-on-chip, networks on chip, synthesis, mapping, architecture.
Citation:
Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli, "NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip," IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, Feb. 2005, doi:10.1109/TPDS.2005.22
Usage of this product signifies your acceptance of the Terms of Use.