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Design and Implementation of a Lossless Parallel High-Speed Data Compression System
June 2004 (vol. 15 no. 6)
pp. 481-490

Abstract—Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. This paper describes the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.

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Index Terms:
Lossless data compression, X-MatchProRli, Multiple Compressors, FPGA.
Citation:
Mark Milward, Jos? Luis N?, David Mulvaney, "Design and Implementation of a Lossless Parallel High-Speed Data Compression System," IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 6, pp. 481-490, June 2004, doi:10.1109/TPDS.2004.7
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