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| Nian-Feng Tzeng, "Multistage-Based Switching Fabrics for Scalable Routers," IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 4, pp. 304-318, April, 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/TPDS.2004.1271180, author = {Nian-Feng Tzeng}, title = {Multistage-Based Switching Fabrics for Scalable Routers}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {15}, number = {4}, issn = {1045-9219}, year = {2004}, pages = {304-318}, doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2004.1271180}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Parallel and Distributed Systems TI - Multistage-Based Switching Fabrics for Scalable Routers IS - 4 SN - 1045-9219 SP304 EP318 EPD - 304-318 A1 - Nian-Feng Tzeng, PY - 2004 KW - Line cards KW - multistage interconnects KW - queue speedups KW - recirculation connections KW - routers KW - routing tags KW - scalability KW - switching fabrics. VL - 15 JA - IEEE Transactions on Parallel and Distributed Systems ER - | |||
Abstract—Rapidly growing demand for high-speed networks has prompted the investigation into scalable routers that are capable of forwarding data at the aggregate rate of multiterabits per second. Such a router contains many line cards (LCs) for admitting external links of various speeds. Those LCs are interconnected by a switching fabric to provide paths for packets to travel from arrival LCs to their respective departure LCs. The switching fabric employed in a router dictates the scalability and the overall performance of the router. It is thus crucial for future multiterabit routers to incorporate scalable switching fabrics capable of interconnecting large numbers of LCs. This work considers switching fabrics with distributed packet routing to achieve high scalability and low costs. Our fabrics are based on a multistage structure with different
[1] S. Bassi et al., Multistage Shuffle Networks with Shortest Path and Deflection Routing for High Performance ATM Switching: The Open-Loop Shuffleout IEEE Trans. Comm., vol. 42, pp. 2881-2889, Oct. 1994.
[2] M. Decina, P. Giacomazzi, and A. Pattavina, Multistage Shuffle Networks with Shortest Path and Deflection Routing for High Performance ATM Switching: The Closed-Loop Shuffleout IEEE Trans. Comm., vol. 42, pp. 3034-3044, Nov. 1994.
[3] S. Blake et al., An Architecture for Differentiated Services Internet IETF RFC 2475, Dec. 1998.
[4] A. Botta et al., The$16 \times 622$Mbits/s COM16M: The PRELUDE Switch Architecture Integrated into a 6-Million Transistor Monochip Proc. 22nd European Solid-State Circuits Conf., Sept. 1997.
[5] H. Chan, H. Alnuweiri, and V. Leung, “A Framework for Optimizing the Cost and Performance of Next-Generation IP Routers,” IEEE J. Selected Areas in Comm., vol. 17, no. 6, pp. 1013-1029, June 1999.
[6] N. Christin, J. Liebeherr, and T. Abdelzaher, A Quantitative Assured Forwarding Service Proc. IEEE INFOCOM'02, pp. 864-873, June 2002.
[7] S. Chuang et al., Matching Output Queuing with a Combined Input Output Queued Switch IEEE J. Selected Areas in Comm., vol. 17, pp. 1030-1039, June 1999.
[8] Cisco Systems, Cisco 12016 Gigabit Switch Router, Data Sheet,http:/www.cisco.com, 2001.
[9] M. Decina, P. Giacomazzi, and A. Pattavina, Shuffle Interconnection Networks with Deflection Routing for ATM Switching: the Open-Loop Shuffleout Proc. 13th Int'l Teletraffic Conf., pp. 27-34, June 1991.
[10] N. Endo, T. Kozaki, T. Ohuchi, H. Kuwahara, and S. Shinobu, "Shared Buffer Memory Switch for an ATM Exchange," IEEE Trans. Comm., vol. 41, no. 1, pp. 237-245, Jan. 1993.
[11] M. Galles, “Spider: A High Speed Network Interconnect” IEEE Micro, vol. 17, no. 1, pp. 34–39 Jan.-Feb. 1997.
[12] A.L. Gupta and N.D. Georganas, Analysis of a Packet Switch with Input and Output Buffers and Speed Constraints Proc. IEEE INFOCOM'91, pp.694-700, Apr. 1991.
[13] M.G. Hluchyj and M.J. Karol, "Queueing in High-Performance Packet Switching," IEEE J. Selected Areas in Comm., vol. 6, pp. 1,587-1,597, Dec. 1988.
[14] M. Katevenis, P. Vatsolaki, and A. Efthymiou, Pipelined Memory Shared Buffer for VLSI Switches Proc. ACM SIGCOMM'95, pp. 39-48, Aug. 1995.
[15] M. Katevenis, D. Serpanos, and E. Spyridakis, Switching Fabrics with Internal Backpressure Using the ATLAS I Single-ChipATM Switch Proc. IEEE GLOBECOM'97, pp. 242-246, Nov. 1997.
[16] N.F. Maxemchuk, "Comparison of Deflection and Store-and-Forward Techniques in the Manhattan Street and Shuffle-Exchange Networks," Proc. INFORCOM '89, vol. 3, pp. 800-809, Apr. 1989.
[17] N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches,” IEEE/ACM Trans. Networking, vol. 7, no. 2, pp. 188-201, Apr. 1999.
[18] N. McKeown et al., "Tiny Tera: A Packet Switch Core," IEEE Micro, Vol. 17, No. 1, Jan.-Feb. 1997, pp. 26-33.
[19] S. Moon, J. Rexford, and K.G. Shin, Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches IEEE Trans. Computers, vol. 49, pp. 1215-1227, Nov. 2000.
[20] A. Pattavina, Performance Evaluation of Batcher-Banyan Interconnection Networks with Output Pooling IEEE J. Selected Areas of Comm., vol. 9, pp. 95-103, Jan. 1991.
[21] M. Pease, III, The Indirect Binaryn-Cube Microprocessor Array IEEE Trans. Computers, vol. 6, no. 5, pp. 250-265, May 1977.
[22] G. Pfister and V. Norton, ‘Hot-Spot’Contention and Combining In Multistage Interconnection Networks IEEE Trans. Computers, vol. 34, no. 10, pp. 943-948, Oct. 1985.
[23] PMC-Sierra Inc., TT1 Chipset, Data Sheet,http:/www.pmc-sierra.com, 1999.
[24] K.J. Schultz and P.G. Culak, CAM-Based Single-Chip Shared Buffer ATM Switch Proc. IEEE Int'l Conf. Comm. (ICC), pp. 1190-1195, June 1994.
[25] I. Stoica and H. Zhang, Providing Guaranteed Services without Per-Flow Management Proc. ACM SIGCOMM'99, pp. 81-94, Aug. 1999.
[26] F.A. Tobagi, T. Kwok, and F.M. Chiussi, "Architecture, Performance, and Implementation of the Tandem Banyan Fast Packet Switch," IEEE J. Selected Areas in Comm., vol. 9, no. 8, pp. 1,173-1,193, 1991.
[27] N. Tzeng and T. Darwish, Implementation of Scalable Switches for Wireless Communications technical report, Center for Advanced Computer Studies, Univ. of Louisiana at Lafayette, 2001.
[28] N. Tzeng, K. Ponnuru, and K. Vibhatavanij, A Cost-Effective Design for ATM Switching Fabrics Proc. 1999 IEEE Int'l Conf. Comm. (ICC), pp. S37.4.1-5, June 1999.
[29] W. Wang, K. Yang, and T. Lin, A Terabit Switch Fabric with Integrated High-Speed CMOS Transceivers Proc. Eighth Symp. High-Performance Interconnects (Hot Interconnects 8), Aug. 2000.
[30] D. Weil et al., A$16 \times 622$Mb/s ATM Switch: PRELUDE Switch Architecture Integrated into a 6-Million Transistor Monochip IEEE J. Solid-State Circuits, vol. 32, pp. 1108-1114, July 1997.
[31] T. Wolf and J. Turner, Design Issues for High-Performance Active Routers IEEE J. Selected Areas in Comm., vol. 19, no. 3, pp. 404-409, Mar. 2001.
[32] P.C. Wong and M.S. Yeung, "Design and Analysis of a Novel Fast Packet Switch—Pipeline Banyan," IEEE/ACM Trans. Networking, vol. 3, no. 1, pp. 63-69, 1995.
[33] H. Yamanaka et al., Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue IEEE J. Selected Areas in Comm., vol. 15, pp. 773-784, June 1997.
[34] K.Y. Yun, A Terabit Multiservice Switch IEEE Micro, vol. 21, no. 1, pp. 58-70, Jan.-Feb. 2001.