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Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times
March 2004 (vol. 15 no. 3)
pp. 273-288
ASCII Text
x 
 
Bharadwaj Veeravalli, Wong Han Min, "Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times," IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 3, pp. 273-288, March, 2004.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2004.1264811,
author = {Bharadwaj Veeravalli and Wong Han Min},
title = {Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {15},
number = {3},
issn = {1045-9219},
year = {2004},
pages = {273-288},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2004.1264811},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times
IS - 3
SN - 1045-9219
SP273
EP288
EPD - 273-288
A1 - Bharadwaj Veeravalli,
A1 - Wong Han Min,
PY - 2004
KW - Linear networks
KW - release times
KW - divisible loads
KW - communication delays
KW - processing times
KW - finish times.
VL - 15
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 

Abstract—The problem of distributing and processing a divisible load in a heterogeneous linear network of processors with arbitrary processors release times is considered. A divisible load is very large in size and has computationally intensive CPU requirements. Further, it has the property that the load can be partitioned arbitrarily into any number of portions and can be scheduled onto processors independently for computation. The load is assumed to arrive at one of the farthest end processors, referred to as boundary processors, for processing. The processors in the network are assumed to have nonzero release times, i.e., the time instants from which the processors are available for processing the divisible load. Our objective is to design a load distribution strategy by taking into account the release times of the processors in such a way that the entire processing time of the load is a minimum. We consider two generic cases in which all processors have identical release times and when all processors have arbitrary release times. We adopt both the single and multi-installment strategies proposed in the divisible load scheduling literature in our design of load distribution strategies, wherever necessary, to achieve a minimum processing time. Finally, when optimal strategies cannot be realized, we propose two heuristic strategies, one for the identical case, and the other for nonidentical release times case, respectively. Several conditions are derived to determine whether or not optimal load distribution exists and illustrative examples are provided for the ease of understanding.

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Index Terms:
Linear networks, release times, divisible loads, communication delays, processing times, finish times.
Citation:
Bharadwaj Veeravalli, Wong Han Min, "Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times," IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 3, pp. 273-288, March 2004, doi:10.1109/TPDS.2004.1264811
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