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Issue No.09 - September (2003 vol.14)
pp: 922-931
ABSTRACT
<p><b>Abstract</b>—The main contribution of this work is to propose an efficient parallel prefix sums architecture based on the recently-developed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores in a network that is fast and highly hardware-compact. The proposed architecture for computing the prefix sums of N-1 bits features a total delay of (4 log N + \sqrt N -2) * T_d, where T_d is the delay for charging or discharging a row of two prefix sum units of eight shift switches. Our simulation results show that, under 0.8-micron CMOS technology, the delay T_d does not exceed 1 ns. As it turns out, our design is faster than any design known to us for values on N in the range 1 \leq N \leq 2^10. Yet, another important and novel feature of the proposed architecture is that it requires very simple controls, partially driven by the semaphores. This significantly reduces the hardware complexity of the design and fully utilizes the inherent speed of the process.</p>
INDEX TERMS
Hardware-algorithms, shift switching, binary prefix sums, binary counting, scalable architectures, VLSI design, domino logic.
CITATION
Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya, "An Efficient Parallel Prefix Sums Architecture with Domino Logic", IEEE Transactions on Parallel & Distributed Systems, vol.14, no. 9, pp. 922-931, September 2003, doi:10.1109/TPDS.2003.1233714