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Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture
May 2003 (vol. 14 no. 5)
pp. 502-515
ASCII Text
x 
 
Allon Adir, Hagit Attiya, Gil Shurek, "Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture," IEEE Transactions on Parallel and Distributed Systems, vol. 14, no. 5, pp. 502-515, May, 2003.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2003.1199067,
author = {Allon Adir and Hagit Attiya and Gil Shurek},
title = {Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {14},
number = {5},
issn = {1045-9219},
year = {2003},
pages = {502-515},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2003.1199067},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture
IS - 5
SN - 1045-9219
SP502
EP515
EPD - 502-515
A1 - Allon Adir,
A1 - Hagit Attiya,
A1 - Gil Shurek,
PY - 2003
KW - Shared memory
KW - multiprocessor systems
KW - PowerPC architecture
KW - models
KW - specification
KW - consistency
KW - synchronization instructions
KW - out-of-order execution.
VL - 14
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 

Abstract—This paper introduces a generic framework for defining instructions, programs, and the semantics of their instantiation by operations in a multiprocessor environment. The framework captures information flow between operations in a multiprocessor program by means of a reads-from mapping from read operations to write operations. Two fundamental relations are defined on the operations: a program order between operations which instantiate the program of some processor and view orders which are specific to each shared memory model. An operation cannot read from the “hidden”past or from the future; the future and the past causality can be examined either relative to the program order or relative to the view orders. A shared memory model specifies, for a given program, the permissible transformation of resource states. The memory model should reflect the programmer's view by citing the guaranteed behavior of the multiprocessor in the interface visible to the programmer. The model should refrain from dictating the design practices that should be followed by the implementation. Our framework allows an architect to reveal the programming view induced by a shared-memory architecture; it serves programmers exploring the limits of the programming interface and guides architecture-level verification. The framework is applicable for complex, commercial architectures as it can capture subtle programming-interface details, exposing the underlying aggressive microarchitecture mechanisms. As an illustration, we define the shared memory model supported by the PowerPC architecture, within our framework.

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Index Terms:
Shared memory, multiprocessor systems, PowerPC architecture, models, specification, consistency, synchronization instructions, out-of-order execution.
Citation:
Allon Adir, Hagit Attiya, Gil Shurek, "Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture," IEEE Transactions on Parallel and Distributed Systems, vol. 14, no. 5, pp. 502-515, May 2003, doi:10.1109/TPDS.2003.1199067
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