This Article 
 Bibliographic References 
 Add to: 
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
May 2002 (vol. 13 no. 5)
pp. 485-498

Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communicate at significantly higher speeds while operating more efficiently to meet system size, weight, power, and energy requirements. As high-performance parallel computing architectures make their way into portable systems, compact, efficient, and error-tolerant computing and communication mechanisms will be required. This paper presents the High-Performance Efficient Router (HiPER), an efficient multidimensional router supporting high-throughput error-corrected communication channels. HiPER is a proof-of-concept vehicle for efficient implementations of routing, switching, and error control mechanisms. It combines mad postman (bit-pipelined) switching with dimension-order routing, producing a low-latency routing router that is less sensitive to message distance than a word parallel crossbar router. To maintain robust communication as link speeds increase and link power budgets decrease, HiPER employs flit-level hop-by-hop retransmission of erroneous flits, which provides built-in error control at the network level. Data presented on the implemented bit serial version of HiPER offer insight into future router designs with channel sizes between bit-serial and word-wide.

[1] H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, Mass.: Addison-Wesley, 1990.
[2] K.K.-Y. Chang, W. Ellersick, T.-S. Chuang, S. Sidiropoulos, and M. Horowitz, “A 2 Gb/s/pin CMOS Asymmetric Serial Link,” Proc. VLSI Circuits Symp., pp. 216-217, June 1998.
[3] R. Farjad-Rad, C.-K.K. Yang, and M. Horowitz, “A 0.3-um CMOS 8-Gb/s 4-PAM Serial Link Transceiver,” J. Solid State Circuits, pp. 757-764, May 2000.
[4] E. Yeung and M. Horowitz, “A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with per Pin Skew Compensation,” Proc. IEEE Int'l Solid State Circuits Conf., pp. 256-257, Feb. 2000.
[5] A.A. Chien, “A Cost and Speed Model for k-Ary n-Cube Wormhole Routers,” Proc. Hot Interconnects '93, Aug. 1993.
[6] W.J. Dally and C.L. Seitz, “The Torus Routing Chip,” J. Distributed Computing, vol. 1, no. 3, pp. 187-196, Oct. 1986.
[7] W.J. Dally and C.L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.
[8] W.J. Dally, "Performance Analysis of k-ary n-Cube Interconnection Networks," IEEE Trans. Computers, vol. 39, no. 6, pp. 775-785, June 1992.
[9] W.J. Dally et al., "Transmitter Equalization for 4-Gbps Signaling," IEEE Micro, Vol. 17, No. 1, Jan.-Feb. 1997, pp. 48-56.
[10] J. Duato, S. Yalamanchili, and L.M. Ni, Interconnection Networks: An Engineering Approach. Los Alamitos, Calif.: IEEE CS Press, 1997.
[11] J.C. Eble, V.K. De, D.S. Wills, and J.D. Meindl, A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001 Proc. Ninth Ann. IEEE Int'l ASIC Conf., pp. 193-196, Sept. 1996.
[12] C.R. Hesshope, P.R. Miller, and J.T. Yanchev, "High Performance Communications in Processor Networks," Proc. Int'l Symp. Computer Architecture, pp. 150-157, 1989.
[13] P. May, M. Lee, S.T. Wilkinson, O. Vendier, Z. Ho, S.W. Bond, D.S. Wills, M. Brooke, N.M. Jokerst, and A. Brown, “A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks,” J. Parallel and Distributed Computing, vol. 41, no. 1 pp. 3-19, Feb. 1997.
[14] P. May, “Enabling Efficient High-Performance Communication in Multicomputer Interconnection Networks,” PhD Dissertation, Dept. of Electronic and Computer Eng., Georgia Inst. of Tech nology, 1999.
[15] E.M. Sentovich, K.J. Singh, L. Lavangno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A System for Sequential Circuit Synthesis,” Electronics Research Laboratory Memorandum no. UDB/ERL M92/41, Dept. of Electrical Eng. and Computer Science, Univ. of California, Berkeley, May 1992.
[16] The International Technology Roadmap for Semiconductors: Technology Needs. Semiconductor Industry Assoc., 1999.
[17] D.S. Wills, H.H. Cat, J.C. Cruz-Rivera, W.S. Lacy, J.M. Baker, J.C. Eble, A.L. Lopez-Lagunas, and M. Hopper, “High-Throughput, Low-Memory Applications on the Pica Architecture,” IEEE Trans. Parallel and Distributed Systems, vol. 8, no. 10, pp. 1055-1067, Oct. 1997.
[18] E. Winkler, “Escape Routing from Chip Scale Packages,” Proc. 1996 IEEE/CPMT Int'l Manufacturing Technology Symp., pp. 393-401, 1996.
[19] C.K.K. Yang et al., "A 0.8-mm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE J. Solid-State Circuits, Vol. 31, No. 12, Dec. 1996, pp. 2,015-2,023.

Index Terms:
Networks, router, mad postman, wormhole routing, dimension-order routing, error control, energy efficient, flit-level retransmission.
Phil May, Santithorn Bunchua, D. Scott Wills, "HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction," IEEE Transactions on Parallel and Distributed Systems, vol. 13, no. 5, pp. 485-498, May 2002, doi:10.1109/TPDS.2002.1003858
Usage of this product signifies your acceptance of the Terms of Use.