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Issue No.12 - December (2001 vol.12)
pp: 1305-1317
ABSTRACT
<p>Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous memory dependences can be overcome by memory dependence speculation which enables a load or store to be speculatively executed before the addresses of all preceding loads and stores are known. Furthermore, multiple speculative stores to a memory location create multiple speculative versions of the location. Program order among the speculative versions must be tracked to maintain sequential semantics. A previously proposed approach, the Address Resolution Buffer (ARB) uses a centralized buffer to support speculative versions. Our proposal, called the Speculative Versioning Cache (SVC), uses distributed caches to eliminate the latency and bandwidth problems of the ARB. The SVC conceptually unifies cache coherence and speculative versioning by using an organization similar to snooping bus-based coherent caches. Our evaluation for the Multiscalar architecture shows that hit latency is an important factor affecting performance and private cache solutions trade-off hit rate for hit latency.</p>
INDEX TERMS
Speculative memory, memory disambiguation, snooping cache coherence protocols, speculative versioning
CITATION
T.N. Vijaykumar, S. Gopal, J.E. Smith, G. Sohi, "Speculative Versioning Cache", IEEE Transactions on Parallel & Distributed Systems, vol.12, no. 12, pp. 1305-1317, December 2001, doi:10.1109/71.970565
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