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Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures
December 2001 (vol. 12 no. 12)
pp. 1293-1304

Very Long Instruction Word (VLIW) architectures can enhance performance by exploiting fine-grained instruction level parallelism. In this paper, we describe a compiler assisted multiple instruction word retry scheme for VLIW architectures. A read buffer is used to resolve the more frequent on-path hazards, while the compiler resolves the remaining branch hazards. Performance evaluation is described for 11 benchmark programs based on the IBM VLIW research compiler, Chameleon. Experimental results indicate that, for a VLIW machine with P functional units to rollback N instruction words, a read buffer of 2NP entries with the compiler assist can be an effective approach in producing low overhead runtime performance and small code growth, for P = 4, 8, 12, and 16 and N \leq 3.

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Index Terms:
Fault-tolerant computing, instruction retry, compilers, VLIW architectures, instruction level parallelism
Citation:
S.-K. Chen, W.K. Fuchs, "Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures," IEEE Transactions on Parallel and Distributed Systems, vol. 12, no. 12, pp. 1293-1304, Dec. 2001, doi:10.1109/71.970564
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