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Issue No.03 - March (2001 vol.12)
pp: 316-335
ABSTRACT
<p><b>Abstract</b>—Many current graphical display systems utilize a buffer memory system to contain a two-dimensional image array to be modified and displayed. In order to speed up the update of the buffer memory system, it is required that the buffer memory system accesses many image points within an image subarray in parallel. This paper proposes an efficient buffer memory system for a fast and high-resolution graphical display system. The memory system provides parallel accesses to <tmath>$pq$</tmath> image points within a <tmath>${\rm{block(p \times q)}}$</tmath>, a <tmath>${\rm{horizontal(1 \times pq)}}$</tmath>, a <tmath>${\rm{vertical(pq \times 1)}}$</tmath>, a forward-diagonal, or a backward-diagonal subarray in a two-dimensional image array, <tmath>${\rm{M \times N}}$</tmath>, where the design parameters <tmath>$p$</tmath> and <tmath>$q$</tmath> are all powers of two. In the address calculation and routing circuit of the proposed buffer memory system, the address differences of the five subarrays are prearranged according to the index numbers of memory modules and stored in two Static Random Access Memories (SRAMs), so that the address differences are simply added to the base address to obtain the addresses according to the index numbers of memory modules. In addition, for the fast address calculation, one single multiplication operation in the base address calculation is replaced by a SRAM access, so that the multiplication operation can be performed during the SRAM access for the address differences for the case when N is not a power of two. The address calculation and routing circuit proposed in this paper is improved in the hardware cost, the complexity of control, and the speed over the previous circuits.</p>
INDEX TERMS
High-resolution graphical display, image processing, buffer memory system, block access, address calculation, address routing, memory module selection.
CITATION
Jong Won Park, "An Efficient Buffer Memory System for Subarray Access", IEEE Transactions on Parallel & Distributed Systems, vol.12, no. 3, pp. 316-335, March 2001, doi:10.1109/71.914779
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