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R. Lin, K. Nakano, S. Olariu, M.C. Pinotti, J.L. Schwing, A.Y. Zomaya, "Scalable HardwareAlgorithms for Binary Prefix Sums," IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 8, pp. 838850, August, 2000.  
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@article{ 10.1109/71.877941, author = {R. Lin and K. Nakano and S. Olariu and M.C. Pinotti and J.L. Schwing and A.Y. Zomaya}, title = {Scalable HardwareAlgorithms for Binary Prefix Sums}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {11}, number = {8}, issn = {10459219}, year = {2000}, pages = {838850}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.877941}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Parallel and Distributed Systems TI  Scalable HardwareAlgorithms for Binary Prefix Sums IS  8 SN  10459219 SP838 EP850 EPD  838850 A1  R. Lin, A1  K. Nakano, A1  S. Olariu, A1  M.C. Pinotti, A1  J.L. Schwing, A1  A.Y. Zomaya, PY  2000 KW  Hardwarealgorithms KW  shift switching KW  binary prefix sums KW  binary counting KW  scalable architectures KW  pipelining. VL  11 JA  IEEE Transactions on Parallel and Distributed Systems ER   
Abstract—In this work, we address the problem of designing efficient and scalable hardwarealgorithms for computing the sum and prefix sums of a
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