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Minimizing Communication in the Bitonic Sort
May 2000 (vol. 11 no. 5)
pp. 459-474

Abstract—This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an $\Omega$-network of $(\log N- 1)$ switch levels. This network reduces the cost complexity to $O(N \log N)$ compared with the $O(N \log^{2} N)$ of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network.

[1] M. Ajtai,J. Komlos,W.L. Steiger, and E. Szemeredi,"An O(n log n) sorting network," Proc. Ann. ACM Symp. Theory of Computing, pp. 1-9, 1983.
[2] S.G. Akl, Parallel Sorting Algorithms.Orlando, Fla.: Academic Press Inc., 1985.
[3] K.E. Batcher, “On Bitonic Sorting Networks,” Proc. 1990 Int'l Conf. Parallel Processing, 1990.
[4] K.E. Batcher, “Sorting Networks and Their Applications,” Proc. Spring Joint Computer Conf., AFIPS, vol. 32, pp. 307-314, 1968.
[5] G.M. Baudet and D. Stevenson, “Optimal Sorting Algorithms for Parallel Computers,” IEEE Trans. Computers, vol. 27, no. 1, pp. 84-87, Jan. 1978.
[6] M. Chien and A. Oru, ”Adaptive Binary Sorting Schemes and Associated Interconnection Networks,” IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 6, June 1994.
[7] S. Fineberg, T. Casavant, and H.J. Siegel, ”Experimental Analysis of a Mixed-Mode Parallel Architecture Using Bitonic Sequence Sorting,” J. Parallel and Distributed Computing, vol. 11, pp. 139-251, Mar. 1991.
[8] M. Flynn, “Very High-Speed Computing Systems,” Proc. IEEE, vol. 54, pp. 1,901-1,909, Dec. 1966.
[9] A. Gottlieb, R. Grishman, C. Kruskal, K. McAuliffe, L. Rudolph, and M. Snir, ”The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer,” IEEE Trans. Computers, vol. 32, no. 2, pp. 175-189, Feb. 1983.
[10] K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability. McGraw-Hill, 1993.
[11] D. Knuth, The Art of Computer Programming, vol. 3: Sorting and Searching. Addison-Wesley, 1973.
[12] M. Kumar and D. Hirschberg, ”An Efficient Implementation of Batcher's Odd-Even Merge Algorithm and Its Application in Parallel Sorting Schemes,” IEEE Trans. Computers, vol. 32, no. 3, pp. 254-264, Mar. 1983.
[13] V. Kumar, A. Grama, A. Gupta, and G. Karypis, Introduction to Parallel Computing: Design and Analysis of Algorithms. Benjamin Cummings, 1994.
[14] D. Lawrie, ”Access and Alignment of Data in an Array Processor,” IEEE Trans. Computers, vol. 24, no. 12, pp. 1,145-1,155, Dec. 1975.
[15] J.-D. Lee, ”Design of General-Purpose Bitonic Sorting Algorithms with a Fixed Number of Processors for Shared-Memory Parallel Computers,” J. KISS(A): Computer Systems and Theory, vol. 26, no. 1, pp. 33-42, 1999.
[16] J.-D. Lee and K.E. Batcher, ”Simplifying Multistage Hardware Interconnection in the Bitonic Sorting Network” Proc. Seventh IASTED/ISMM Int'l Conf. Parallel and Distributed Computing and Systems, pp. 138-142, 1995.
[17] J.-D. Lee and K.E. Batcher, ”A Bitonic Sorting Network with Simpler Flip-Interconnections,” Proc. I-SPAN '96: Int'l Symp. Parallel Architectures, Algorithms, and Networks, pp. 104-109, 1996.
[18] J.-D. Lee and K.E. Batcher, ”Minimizing Communication of a Recirculating Bitonic Sorting Network,” Proc. 25th Int'l Conf. Parallel Processing, vol. I, pp. I-251-254, 1996.
[19] T. Leighton, "Tight Bounds on the Complexity of Parallel Sorting," IEEE Trans. Computers, vol. 34, no. 4, pp. 344-354, Apr. 1985.
[20] K. Liszka, ”Generalized Bitonic and Odd-Even Merging Networks,” doctoral dissertation, Dept. of Math. and Computer Science, Kent State Univ., 1992.
[21] D. Nassimi and S. Sahni, ”Bitonic Sort on a Mesh-Connected Parallel Computer,” IEEE Trans. Computers, vol. 27, no. 1, pp. 2-7, Jan. 1979.
[22] T. Nakatani, S.-T. Huang, B.W. Arden, and S.K. Tripathi, "K-Way Bitonic Sort," IEEE Trans. Computers, vol. 38, no. 2, pp. 283-288, Feb. 1989.
[23] S. Orcutt, ”Implementation of Permutation Functions in ILLIAC IV Type Computers,” IEEE Trans. Computers, vol. 25, no. 9, pp. 929-936, 1976.
[24] M.S. Paterson, ”Improved Sorting Networks with$O(\log N)$Depth,” Algorithmica, vol. 5, pp. 75-92, 1990.
[25] M.J. Quinn, Parallel Computing: Theory and Practice.New York: McGraw-Hill, 1994.
[26] H.J. Siegel, Interconnection Networks for Large-Scale Parallel Processing, Second Ed., McGraw-Hill, New York, 1990.
[27] H. Siegel, ”The Universality of Various Types of SIMD Machine Interconnection Networks,” Proc. Fourth Ann. Symp. Computer Architecture, pp. 23-25, 1977.
[28] H.S. Stone, ”Parallel Processing with the Perfect Shuffle,” IEEE Trans. Computers, vol. 20, pp. 153-161, Feb. 1971.
[29] C. Thompson and H. Kung,“Sorting on a mesh connected parallel computer,”Commun. ACM, vol. 20, pp. 263–271, 1977.
[30] B. Wang, G. Chen, and C. Hsu, ”Bitonic Sort with an Arbitrary Number of Keys,” Proc. 1991 Int'l Conf. Parallel Processing, vol. 3, pp. 58-61, 1991.

Index Terms:
Bitonic sorting, parallel computing, sorting networks, omega networks, sorting, minimizing communication.
Jae-Dong Lee, Kenneth E. Batcher, "Minimizing Communication in the Bitonic Sort," IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 5, pp. 459-474, May 2000, doi:10.1109/71.852399
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