This Article 
 Bibliographic References 
 Add to: 
Tighter Layouts of the Cube-Connected Cycles
February 2000 (vol. 11 no. 2)
pp. 182-191

Abstract—Preparata and Vuillemin proposed the cube-connected cycles (${\cal {CCC}}$) and its compact layout in 1981 [17]. We give a new layout of the ${\cal {CCC}}$ which uses less than half the area of the Preparata-Vuillemin layout. We also give a lower bound on the layout area of the ${\cal {CCC}}$. The area of the new layout deviates from this bound by a small constant factor. If we “unfold” the cycles in the ${\cal {CCC}}$, the resulting structure can be laid out in optimal area.

[1] F.S. Annexstein, M. Baumslag, and A.L. Rosenberg, “Group Action Graphs and Parallel Architectures,” SIAM J. Computing, vol. 19 pp. 544-569, 1990.
[2] A. Avior, T. Calamoneri, S. Even, A. Litman, and A.L. Rosenberg, “A Tight Layout of the Butterfly Network,” Theory of Computing Systems, vol. 31, no. 4, pp. 475-488, 1998.
[3] K.E. Batcher, “The Flip Network in STARAN,” Proc. Int'l Conf. Parallel Processing, pp. 65–71, 1976.
[4] R. Beigel and C.P. Kruskal, "Processor Networks and Interconnection Networks without Long Wires," Proc. First ACM Symp. Parallel Algorithms and Architectures, pp. 42-51, 1989.
[5] S.N. Bhatt and F.T. Leighton, “A Framework for Solving VLSI Graph Layout Problem,” J. Computer and System Sciences, vol. 28, no. 2, pp. 300–343, 1984.
[6] N. Blum, “An Area-Maximum Edge Length Tradeoff for VLSI Layout,” Information and Control, vol. 66,no. 1/2, pp. 45-52, 1984.
[7] G. Chen and F.C.M. Lau, Layout of CCC without Long Wires, Technical Report 97-09, Dept. of Computer Science and Information Systems, University of Hong Kong, 1997.
[8] G. Chen and F.C.M. Lau, “Comments on a New Family of Cayley Graph Interconnection Networks of Constant degree Four,” IEEE Trans. Parallel and Distributed Systems, vol. 8, no. 12, pp. 1,299-1,300, Dec. 1997.
[9] Y. Dinitz, A Compact Layout of Butterfly on the Square Grid, Technical Report 873, Technion-Israel Inst. of Technology, Haifa, Israel, Nov. 1995.
[10] R. Feldmann and W. Unger, “The Cube-Connected Cycles Network Is a Subgraph of the Butterfly Network,” Parallel Processing Letters, vol. 2, no. 1, pp. 13-19, 1992.
[11] C.P. Kruskal and M. Snir, “A Unified Theory of Interconnection Network Structure,” Theoretical Computer Science, vol. 48, pp. 75-94, 1986.
[12] F.C.M. Lau and G. Chen, “Optimal Layouts of Midimew Networks,” IEEE Trans. Parallel and Distributed Systems, vol. 7, no. 9, pp. 954–961, Sept. 1996.
[13] F.T. Leighton, Complexity Issues in VLSI: Optimal Layout for the Shuffle-Exchange Graph and Other Networks. MIT Press, 1983.
[14] F.T. Leighton,Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes.San Mateo, Calif.: Morgan Kaufmann, 1992.
[15] C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, Reading, Mass., 1980.
[16] K. Mehlhorn, F. P. Preparata, and M. Sarrafzadeh, “Channel Routing in Knock-Knee Mode: Simplified Algorithms and Proofs,” Algorithmica, vol. 1, pp. 213–221, 1986.
[17] F.P. Preparata and J. Vuillemin, “The Cube-Connected Cycles: A Versatile Network for Parallel Computation,” Comm ACM, vol. 24, no. 5, pp. 300-309, 1981.
[18] C.D. Thompson, "Area-Time Complexity for VLSI," Proc. 11th Ann. Symp. Theory of Computing, pp. 81-88, 1979.
[19] C.D. Thompson,“A complexity theory for VLSI,” PhD thesis, Carnegie-Mellon Univ., Aug. 1980.
[20] D.S. Wise, “Compact Layouts of Banyan/FFT Networks,” VLSI Sytems and Computations, H.T. Kung, R. Sproull, and G. Steele, eds., pp. 186–195, Springer-Verlag, 1981.

Index Terms:
Interconnection networks, cube-connected cycles, VLSI, embedding, routing, layout.
Guihai Chen, Francis C.M. Lau, "Tighter Layouts of the Cube-Connected Cycles," IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 2, pp. 182-191, Feb. 2000, doi:10.1109/71.841753
Usage of this product signifies your acceptance of the Terms of Use.