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Issue No.03 - March (1999 vol.10)

pp: 266-280

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.755826

ABSTRACT

<p><b>Abstract</b>—The first main contribution of this work is to propose an efficient VLSI architecture obtained by augmenting the Mesh with Multiple Broadcasting (MMB) with precharged 1-bit row and column buses. The new architecture, which we call Mesh with Hybrid Buses (MHB for short), is realizable in VLSI with no increase in the area or the wiring complexity of the MMB chip. Our second main contribution is to show that the MHB is extremely well-suited for solving an entire slew of digital geometry tasks. The MHB is not a reconfigurable architecture. Yet, quite remarkably, for a large number of fundamental digital geometry tasks, the MHB offers a level of performance previously attained only by reconfigurable architectures. Specifically, with a digital image pretiled onto a MHB of size <tmath>$\sqrt n \times \sqrt n$</tmath> one pixel per processor, we show that the problems of computing the convex hull of the image, computing the diameter and the width of the image, deciding whether a set of digital points is a digital line, computing the maximum distance between two images, deciding whether two images are linearly separable, computing several moments and low-level descriptors of the image, including the perimeter, area, center, and median row of its convex hull, can be solved in <tmath>$O(\log n)$</tmath> time. By contrast, the fastest possible algorithms for the problems above on the MMB run in <tmath>$\Theta(n^{1/6})$</tmath> time. Finally, we go on to show that, with minor changes, our algorithms can be implemented to run within cost-optimality on a MHB of size <tmath>${\frac{\sqrt n}{\log n}} \times {\frac{\sqrt n}{\log n}}$</tmath>.</p>

INDEX TERMS

VLSI architectures, broadcasting, mesh with hybrid buses, digital geometry, image processing, pattern recognition, cellular systems, cost-optimal algorithms.

CITATION

S. Olariu, R. Lin, B.-f. Wang, "The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry",

*IEEE Transactions on Parallel & Distributed Systems*, vol.10, no. 3, pp. 266-280, March 1999, doi:10.1109/71.755826