This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Computer Vision Algorithms on Reconfigurable Logic Arrays
January 1999 (vol. 10 no. 1)
pp. 29-43

Abstract—Computer vision algorithms are natural candidates for high performance computing systems. Algorithms in computer vision are characterized by complex and repetitive operations on large amounts of data involving a variety of data interactions (e.g., point operations, neighborhood operations, global operations). In this paper, we describe the use of the custom computing approach to meet the computation and communication needs of computer vision algorithms. By customizing hardware architecture at the instruction level for every application, the optimal grain size needed for the problem at hand and the instruction granularity can be matched. A custom computing approach can also reuse the same hardware by reconfiguring at the software level for different levels of the computer vision application. We demonstrate the advantages of our approach using Splash 2—a Xilinx 4010-based custom computer.

[1] U.S. National Science Foundation, "Grand Challenge: High-Performance Computing and Communications," Report of the Committee on Physical, Mathematical, and Eng. Sciences, U.S. Office of Science and Technology Policy, U.S. Nat'l Science Foundation, Washington, D. C., 1992.
[2] P. Kahn, "Building Blocks for Computer Vision Systems," IEEE Expert, vol. 8, no. 6, pp. 40-50, Dec. 1993.
[3] C.C. Weems, "Architectural Requirements of Image Understanding with Respect to Parallel Processing," Proc. IEEE, vol. 79, no. 4, pp. 537-547, Apr. 1991.
[4] A.N. Choudhary, J.H. Patel, and N. Ahuja, "NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems," IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 10, pp. 1,092-1,104, Oct. 1993.
[5] C.C. Weems, S.P. Levitan, A.R. Hanson, E.M. Riseman, D.B. Shu, and J.G. Nash, "The Image Understanding Architecture," Int'l J. Computer Vision, vol. 2, no. 3, pp. 251-282, 1989.
[6] L. Geppert, "Technology 1998: Solid state," IEEE Spectrum, vol. 35, no. 1, pp. 23-28, Jan. 1998.
[7] D.W. Hammerstrom and D.P. Lulich, "Image Processing Using One-Dimensional Processor Arrays," Proc. IEEE, vol. 84, no. 7, pp. 1,005-1,018, July 1996.
[8] J.D. Crisman and J.A. Webb, "The Warp Machine on Navlab," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 13, no. 5, pp. 451-465, May 1991.
[9] P. Baglietto, M. Marseca, M. Migliardi, and N. Zingrian, "Image Processing on High-Performance RISC Systems," Proc. IEEE, vol. 84, no. 7, pp. 917-930, July 1996.
[10] C.-L. Wang, P.B. Bhat, and V.K. Prasanna, "High-Performance Computing for Vision," Proc. IEEE, vol. 84, no. 7, pp. 931-946, July 1996.
[11] M.H. Sunwoo and J.K. Aggarwal, "VisTA—An Image Understanding Architecture," Parallel Architectures and Algorithms for Image Understanding, V.K. Prasanna Kumar, ed., pp. 121-153.San Diego, Calif.: Academic Press, 1991.
[12] D. Chin et al., “The Princeton Engine: A Real‐Time Video System Simulator,” IEEE Trans. Consumer Electronics, Vol. 34, No. 2, 1988, pp. 285–297.
[13] V. Chaudhary and J.K. Aggarwal, "Parallelism in Computer Vision: A Review," Parallel Algorithms for Machine Intelligence and Vision, V. Kumar, P.S. Gopalkrishnan, and L.N. Kanal, eds., pp. 271-309.New York: Springer-Verlag, 1990.
[14] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[15] J. Rose, A. El Gammal, and A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays," Proc. IEEE, vol. 81, no. 7, pp. 1,013-1,029, July 1993.
[16] Splash 2: FPGAs for Custom Computing Machines, D.A. Buell, J.M. Arnold, and W.J. Kleinfelder, eds. Los Alamitos, Calif.: IEEE CS Press, 1996.
[17] M.J. Wirthlin and B.L. Hutchings, “A Dynamic Instruction Set Computer,” Proc. IEEE Workshop FPGAs for Custom Computing Machines, pp. 99-107, Apr. 1995.
[18] D. Burger and J. Goodman, "Billion-Transistor Architectures," Computer, Sept. 1997, pp. 46-47.
[19] E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarsinghe, and A. Agarwal, "Baring It All to Software: Raw Machines," Computer, vol. 30, no. 6, pp. 66-71, June 1997.
[20] D.T. Hoang, "Searching Genetic Databases on Splash 2," Proc. IEEE Workshop FPGAs for Custom Computing Machines,Napa, Calif., 1993.
[21] P. Bertin, D. Roncin, and J. Vuillemin, "Programmable Active Memories: A Performance Assessment," Research on Integrated Systems, G. Borriello and C. Ebeling, eds., pp. 88-102.Cambridge, Mass.: MIT Press, 1993.
[22] P.M. Athanas and A.L. Abbott, "Real-Time Image Processing on a Custom-Computing Platform," Computer, vol. 28, no. 2, pp. 16-24, Feb. 1995.
[23] C.E. Cox and E. Blanz, "GANGLION—A Fast Field-Programmable Gate Array Implementation of a Connectionist Classifier," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 288-299, Mar. 1992.
[24] N.K. Ratha, "Computer Vision Algorithms on Reconfigurable Logic Arrays," PhD thesis, Michigan State Univ., 1996.
[25] P.K. Chan and S. Mourad, Digital Design Using Field Programmable Gate Arrays, Prentice-Hall, Englewood Cliffs, N.J., 1994.
[26] P.M. Athanas and H.F. Silverman, “Processor Reconfiguration through Instruction-Set Metamorphosis,” Computer, vol. 26, no. 3, pp. 11-18, Mar. 1993.
[27] R. Amerson, R. Carter, B. Culbertson, P. Kuekes, and G. Snider, "Teramac-Configurable Custom Computing," D.A. Buell and K.L. Pocek, eds., Proc. IEEE Workshop on FPGAs for Custom Computing Machines,Napa, Calif., Apr. 1998, pp. 32-38.
[28] Proc. FPGAs for Custom Computing Machines,Napa Valley, Calif., Apr. 1993.
[29] Proc. FPGAs for Custom Computing Machines.Napa Valley, Calif., Apr. 1994.
[30] Proc. FPGAs for Custom Computing Machines,Napa Valley, Calif., Apr. 1995.
[31] J. Villasenor and W.H. Mangione-Smith, "Configurable Computing," Scientific Am., vol. 30, no. 9, pp. 46-48, Sept. 1997.
[32] W. Mangione-Smith, B. Hutchins, D.L. Andrews, A. DeHon, C. Ebeling, R.W. Hartenstein, O. Mencer, J.M. Krishna, V. Palem, V.K. Prasanna, and H.A.E. Spaanenburg, “Seeking Solutions in Configurable Computing,” Computer, vol. 30, no. 12, pp. 38-43, Dec. 1997.
[33] D.H. Ballard and C.M. Brown, Computer Vision, Prentice Hall, Upper Saddle River, N.J., 1982.
[34] Z. Fang, X. Li, and L.M. Ni, "On the Communication Complexity of Generalized 2D Convolution on Array Processors," IEEE Trans. Computers, vol. 38, no. 2, pp. 184-194, Feb. 1989.
[35] H.T. Kung, L.M. Ruane, and D.W.L. Yen, "A Two-Level Pipelined Systolic Array for Convolutions," VLSI Systems and Computations, H.T. Kung, B. Sproull, and G. Steele, eds., pp. 255-264.Maryland: Computer Science Press, 1981.
[36] S. Ranka and S. Sahni, "Convolution on Mesh Connected Multicomputers," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 12, no. 3, pp. 315-318, Mar. 1990.
[37] J.H. Chang, O.H. Ibarra, T. Pong, and S.M. Sohn, "Two-Dimensional Convolution on a Pyramid Computer," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 10, no. 4, pp. 590-593, July 1988.
[38] C. Chakrabarti and J. Jaja, "VLSI Architectures for Template Matching and Block Matching," Parallel Architectures and Algorithms for Image Understanding, V.K. Prasanna Kumar, ed., pp. 3-27.San Diego, Calif.: Academic Press, 1991.
[39] N.K. Ratha, A.K. Jain, and D.T. Rover, "Convolution on Splash 2," Proc. IEEE Symp. FPGAs for Custom Computing Machines, pp. 204-213,Napa Valley, Calif., 1995.
[40] V.K. Prasanna, C.-L. Wang, and A.A. Khokhar, "Low Level Vision Processing on Connection Machine CM-5," Proc. IEEE Workshop Computer Architecture for Machine Perception, pp. 117-126,New Orleans, Dec. 1993.
[41] J.N. Patel, A.A. Khokhar, and L.H. Jameison, "Implementation of Parallel Image Processing Algorithms in the CLONER Environment," Proc. IEEE Workshop VLSI Signal Processing, pp. 83-92,La Jolla, Calif., Oct. 1994.
[42] MaxVideo 250. Datacube Inc., 1995.
[43] N.K. Ratha, A.K. Jain, and D.T. Rover, "FPGA-Based High Performance Page Layout Segmentation," Proc. IEEE Great Lakes Symp. VLSI, pp. 29-34,Ames, Iowa, Mar. 1996.
[44] N.R. Pal and S.K. Pal, "A Review on Image Segmentation Techniques," Pattern Recognition, vol. 26, no. 9, pp. 1,277-1,294, Sept. 1993.
[45] A.K. Jain and Y. Zhong, "Page Layout Segmentation Based on Texture Analysis," Proc. Second Int'l Conf. on Image Processing, pp. 308-311,Washington, D.C., Oct. 1995.
[46] A.K. Jain and K. Karu, “Learning Texture Discrimination Masks,” IEEE Trans. Pattern Analysis Machine Intelligence, vol. 18, no. 2, pp. 195-205, Feb. 1996.
[47] N.K. Ratha and A.K. Jain, "High Performance Custom Computing for Image Segmentation," High Performance Computing Conf., pp. 67-72,New Delhi, India, Dec. 1995.
[48] T. Nordstrom and B. Svensson, "Using and Designing Massively Parallel Computers for Artificial Neural Networks," J. Parallel and Distributed Computing, vol. 14, pp. 260-285, 1992.
[49] N.B. Serbedzija, "Simulating Artificial Neural Networks on Parallel Architecture," Computer, vol. 29, no. 3, pp. 56-63, Mar. 1996.
[50] S.L. Bade and B.L. Hutchings, "FPGA-Based Stochastic Neural Networks Implementation," Proc. Second IEEE Workshop FPGAs for Custom Computing Machines, D.A. Buell and K.L. Poeck, eds., pp. 189-199,Napa Valley, Calif., 1994.
[51] B. Miller, "Vital Signs of Identity," IEEE Spectrum, Feb. 1994, pp. 22-30.
[52] The Science of Fingerprints: Classification and Uses. Federal Bureau of Investigation, U.S. Government Printing Office, Washington, D.C., 1984.
[53] N. Ratha, K. Karu, S. Chen, and A.K. Jain, "A Real-Time Matching System for Large Fingerprint Databases," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 18, no. 8, pp. 799-813, Aug. 1996.

Index Terms:
Reconfigurable computing, computer vision, image processing, image segmentation, neural networks, fingerprint matching.
Citation:
Nalini K. Ratha, Anil K. Jain, "Computer Vision Algorithms on Reconfigurable Logic Arrays," IEEE Transactions on Parallel and Distributed Systems, vol. 10, no. 1, pp. 29-43, Jan. 1999, doi:10.1109/71.744833
Usage of this product signifies your acceptance of the Terms of Use.