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A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems
June 1998 (vol. 9 no. 6)
pp. 601-608

Abstract—In parallel processor systems, the performance of individual processors is a key factor in overall performance. Processor performance is strongly affected by the behavior of cache memory in that high hit rates are essential for high performance. Hit rates are lowered when collisions on placing lines in the cache force a cache line to be replaced before it has been used to best effect. Spatial cache collisions occur if data structures and data access patterns are misaligned. We describe a mathematical scheme to improve alignment and enhance performance in applications which have moderate-to-large numbers of arrays, where various dimensionalities are involved in localized computation and array access patterns are sequential. These properties are common in many computational modeling applications. Furthermore, the scheme provides a single solution when an application is targeted to run on various numbers of processors in power-of-two sizes. The applicability of the proposed scheme is demonstrated on testbed code for an air quality modeling problem.

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Index Terms:
Cache collision, cache offset, direct-mapped cache, highly parallel systems, sequential DO-loops.
Citation:
David C. Wong, Edward W. Davis, Jeffrey O. Young, "A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems," IEEE Transactions on Parallel and Distributed Systems, vol. 9, no. 6, pp. 601-608, June 1998, doi:10.1109/71.689447
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