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Issue No.10 - October (1997 vol.8)
pp: 1055-1067
<p><b>Abstract</b>—This paper describes Pica, a fine-grain, message-passing architecture designed to efficiently support high-throughput, low-memory parallel applications, such as image processing, object recognition, and data compression. By specializing the processor and reducing local memory (4,096 36-bit words), multiple nodes can be implemented on a single chip. This allows high-performance systems for high-throughput applications to be realized at lower cost. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task manager support fast task swapping. Fixed-sized activation contexts simplify storage management. Word-tag synchronization bits provide low-cost synchronization. Several applications have been developed for this architecture, including thermal relaxation, matrix multiplication, JPEG image compression, and Positron Emission Tomography image reconstruction. These applications have been executed using an instrumented instruction-level simulator. The results of these experiments and an evaluation of Pica's architectural features are presented.</p>
Fine-grain parallelism, image processing architectures, through-wafer interconnects, MIMD architectures.
D. Scott Wills, Huy H. Cat, José Cruz-Rivera, W. Stephen Lacy, James M. Baker, John C. Eble, Abelardo López-Lagunas, Michael Hopper, "High-Throughput, Low-Memory Applications on the Pica Architecture", IEEE Transactions on Parallel & Distributed Systems, vol.8, no. 10, pp. 1055-1067, October 1997, doi:10.1109/71.629488
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