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Rumen Andonov, Sanjay Rajopadhye, "Knapsack on VLSI: from Algorithm to Optimal Circuit," IEEE Transactions on Parallel and Distributed Systems, vol. 8, no. 6, pp. 545561, June, 1997.  
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@article{ 10.1109/71.595572, author = {Rumen Andonov and Sanjay Rajopadhye}, title = {Knapsack on VLSI: from Algorithm to Optimal Circuit}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {8}, number = {6}, issn = {10459219}, year = {1997}, pages = {545561}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.595572}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Parallel and Distributed Systems TI  Knapsack on VLSI: from Algorithm to Optimal Circuit IS  6 SN  10459219 SP545 EP561 EPD  545561 A1  Rumen Andonov, A1  Sanjay Rajopadhye, PY  1997 KW  Application specific VLSI design KW  systolic arrays KW  unbounded knapsack problem KW  spacetime transformations KW  recurrence equations KW  dynamic dependencies KW  nonlinear discrete optimization KW  correctness preserving transformations. VL  8 JA  IEEE Transactions on Parallel and Distributed Systems ER   
Abstract—We present a parallel solution to the unbounded knapsack problem on a linear systolic array. It achieves optimal speedup for this wellknown, NPhard problem on a model of computation that is weaker than the PRAM. Our array is correct by construction, as it is formally derived by transforming a recurrence equation specifying the algorithm.
This recurrence has dynamic dependencies, a property that puts it beyond the scope of previous methods for automatic systolic synthesis. Our derivation thus serves as a case study. We generalize the technique and propose a systematic method for deriving systolic arrays by nonlinear transformations of recurrences. We give sufficient conditions that the transformations must satisfy, thus extending systolic synthesis methods.
We address a number of pragmatic considerations: implementing the array on only a fixed number of PEs, simplifying the control to just two counters and a few latches, and loading the coefficients so that successive problems can be pipelined without any loss of throughput.
Using a register level model of VLSI, we formulate a nonlinear optimization problem to minimize the expected running time of the array. The analytical solution of this problem allows us to choose the memory size of each PE in an optimal manner.
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