This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Circuit Switching with Input Queuing: An Analysis for the d-Dimensional Wraparound Mesh and the Hypercube
April 1997 (vol. 8 no. 4)
pp. 349-366

Abstract—We analyze circuit switching in a multiprocessor network, where connection requests (or sessions) arrive at each node of the network according to a Poisson process with rate λ. Each session joins the appropriate input-queue at its source node, and, upon advancing to the head of the queue, transmits a setup packet to establish a connection. If the setup packet is successful, it reserves the links on the path for the duration of the session, and the session is served without interruptions. Otherwise, the connection request remains queued at the source, and subsequent attempts are made to establish the circuit. We analyze the queue of connection requests at the input-buffer of a network link, and obtain analytic expressions for the stability region, the average queuing delay, the average connection time, the average waiting time, and the average total delay, which show how these parameters depend on system variables, such as network dimension and session arrival rate. The queuing analysis focuses on the input-queue of a particular link, and accounts for the interactions with queues of other links through the retrial attempts and the associated probability of success. The queuing analysis is independent of the particular network topology under consideration, as long as the probability that a session arriving at a random time successfully establishes a connection can be calculated for that network. Simulations demonstrate the close agreement between the observed network behavior and that predicted by the analysis.

[1] S. Abraham and K. Padmanabhan, "Performance of the Direct Binary n-Cube Network for Multiprocessors," IEEE Trans. Computers, vol. 38, no. 7, pp. 1000-1011, July 1989.
[2] W.A. Aiello, F.T. Leighton, B.M. Maggs, and M. Newman, "Fast Algorithms for Bit-Serial Routing on a Hypercube," Mathematical Systems Theory, vol. 24, no. 4, pp. 253-271, Apr. 1991.
[3] D. Bertzekas and R. Gallager, Data Networks, second ed. Prentice-Hall, 1992.
[4] C. Bruno and T. Salvatore, "On Modeling Link Conflict Resolution Strategies for Circuit-Switching Hypercubes," Proc. Advanced Computer Technology, Reliable Systems, and Applications, Fifth Ann. European Computer Conf., CompEuro '91, pp. 662-666, May 1991.
[5] L.N. Bhuyan,Q. Yang, and D.P. Agrawal,"Performance of Multiprocessor Interconnection Networks," Computer, vol. 22, no. 2, pp. 25-37, Feb. 1989.
[6] G.-M. Chiu, C.S. Chalsani, and C.S. Raghvendra, "Flexible Routing Criteria for Circuit-Switched Hypercubes," J. Parallel and Distributed Computing, vol. 22, no. 2, pp. 279-284, Aug. 1994.
[7] I. Chlamtac, A. Ganz, and M. Kienzle, "A Performance Model of a Connection Based Hypercube Interconnection System," Proc. Fifth Int'l Conf. Computer Performance Evaluation, Modeling Techniques and Tools, pp. 215-218,Torino, Italy, Feb.13-15, 1991.
[8] S.B. Choi and A.K. Somani, "Rearrangeable Circuit-Switched Architectures for Routing Permutations," J. Parallel and Distributed Computing, vol. 19, no. 2, pp. 125-130, Oct. 1993.
[9] M.A. Csoppenszky and A.K. Somani, "Efficient Distributed Routing Algorithms for a Synchronous Circuit-Switched Hypercube," Proc. Int'l Phoenix Conf. Computers and Comm., pp. 15-22,Scottsdale, Ariz., Apr.1-3, 1992.
[10] W.J. Dally, "Performance Analysis of k-ary n-Cube Interconnection Networks," IEEE Trans. Computers, vol. 39, no. 6, pp. 775-785, June 1992.
[11] W.J. Dally and C.L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.
[12] P.T. Gaughan and S. Yalamanchili, "Analytical Models of Bandwidth Allocation in Pipelined k-Ary n-Cubes," Proc. Seventh Int'l Parallel Processing Symp., Apr. 1993.
[13] D.C. Grunwald and D.A Reed, "Networks for Parallel Processors: Measurements and Prognostications," Proc. Conf. Hypercube Multiprocessors, pp. 610-619,Pasadena, Calif., Jan. 1988.
[14] D.C. Grunwald and D.A. Reed, "Analysis of Backtracking Routing in Binary Hypercube Computers," Research Report UIUCDCS-R-89-1486, Dept. of Computer Science, Univ. of Illi nois, Urbana-Champaign, Feb. 1989.
[15] L. Kleinrock, Queuing Systems-Volume I: Theory.New York: John Wiley and Sons, 1975.
[16] C.P. Kruskal and M. Snir, "The Performance of Multistage Interconnection Networks for Multiprocessors," IEEE Trans. Computers, vol. 32, no. 12, pp. 1,091-1,098, Dec. 1983.
[17] D. Reed and R. Fujimoto, Multicomputer Networks: Message-Based Parallel Processing. MIT Press, 1987.
[18] D.A. Reed and D.C. Grunwalk, "The Performance of Multicomputer Interconnection Networks," Computer, vol. 20, no. 6, pp. 63-73, June 1987.
[19] A. Youssef, "Online Communication on Circuit-Switched Fixed Routing Meshes," Proc. Sixth Int'l Parallel Processing Symp.,Beverly Hills, Calif., pp. 390-397, Mar.23-26, 1992.

Index Terms:
Circuit switching, input queuing, interconnection networks, wraparound meshes, hypercubes, queuing delay, connection delay, stability region.
Citation:
Vishal Sharma, Emmanouel A. Varvarigos, "Circuit Switching with Input Queuing: An Analysis for the d-Dimensional Wraparound Mesh and the Hypercube," IEEE Transactions on Parallel and Distributed Systems, vol. 8, no. 4, pp. 349-366, April 1997, doi:10.1109/71.588603
Usage of this product signifies your acceptance of the Terms of Use.