This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Designing Clustered Multiprocessor Systems under Packaging and Technological Advancements
September 1996 (vol. 7 no. 9)
pp. 962-978

Abstract—Clustered or hierarchical interconnections demonstrate advantage in designing large scale multiprocessor systems. Earlier studies in literature have either focused on only flat interconnections or proposed hierarchical/clustered interconnections with limited packaging and demanded performance constraints. Large systems require several levels of packaging. Packaging technologies impose various physical constraints on bisection bandwidth and channel width of a system. Pinout technologies and capacity of packaging modules have been ignored in earlier studies, often leading to configurations that are not design-feasible. Similarly, the impact of processor and interconnect technologies on demanded performance has also not been considered. In this paper, we propose a new supply-demand framework for multiprocessor system design by considering packaging, processor, and interconnect technologies in an integrated manner. The elegance of this framework lies in its parameterized representation of different technologies. For a given set of technological parameters the framework derives the best configuration while considering practical design aspects like maximum board area, maximum available pinout, fixed channel width, and scalability. In order to build a scalable parallel system with a given number of processors, the framework explores the design space of flat k-ary n-cube topologies and their clustered variations (k-ary n-cube cluster-c) to derive design-feasible configurations with best system performance. The study identifies processor board area, supported channel width, board pinout density, and router pinout as critical parameters and analyzes their impact on deriving design-feasible and best configurations. For a wide range of parameters, it is shown that best configurations are achieved with cluster-based systems with up to 8 processors per cluster and 3D-5D intercluster interconnection.

[1] S. Abraham and K. Padmanabhan, "Constraint Based Evaluation of Multicomputer Networks," Proc. Int'l Conf. Parallel Processing, pp. 521-525, Aug. 1990.
[2] A. Agarwal, "Limits on Interconnection Network Performance," IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 4, pp. 398-412, Oct. 1991.
[3] A. Asthana, H. Jagdish, and B. Mathews, "Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer," Proc. Int'l Conf. Parallel Processing, pp. 323-327, Aug. 1989.
[4] D. Basak and D.K. Panda, "Scalable Architectures with k-ary n-cube Cluster-c Organization," Proc. Symp. Parallel and Distributed Processing, pp. 780-787, 1993.
[5] D. Basak and D.K. Panda, "Designing Large Hierarchical Multiprocessor Systems under Processor, Interconnection, and Packaging Advancements," Proc. Int'l Conf. Parallel Processing, pp. I:63-66, 1994.
[6] D. Basak and D.K. Panda, "Designing Clustered Multiprocessor Systems under Packaging and Technological Advancements," Technical Report OSU-CISRC-11/95-TR51, Dept. of Computer and Information Science, Ohio State Univ., 1995.
[7] Cray Reasearch Inc, Cray T3D System Architecture Overview, 1993.
[8] W.J. Dally, "Performance Analysis of k-ary n-Cube Interconnection Networks," IEEE Trans. Computers, vol. 39, no. 6, pp. 775-785, June 1992.
[9] S.P. Dandamudi and D.L. Eager, "Hierarchical Interconnection Networks for Multicomputer Systems," IEEE Trans. Computers, pp. 786-797, 1990.
[10] D. Lenoski et al., “The Stanford DASH Multiprocessor,” Computer, pp. 63-79, Mar. 1992.
[11] W. Hsu and P.C. Yew, "The Performance of Hierarchical Systems with Wiring Constraints," Proc. Int'l Conf. Parallel Processing, pp. 9-16, Aug. 1991.
[12] W. Hsu and P.C. Yew, "The Impact of Wiring Constraints on Hierarchical Network Performance," Proc. Int'l Parallel Processing Symp., pp. 580-588, Mar. 1992.
[13] Intel Corporation, Paragon XP/S Product Overview, 1991.
[14] M.D. Noakes, D.A. Wallach, and W.J. Dally, "The J-Machine Multicomputer: An Architectural Evaluation," Proc. 20th Ann. Int'l Symp. Computer Architecture, pp. 224-235, May 1993.
[15] K. Padmanabhan, "Efficient Architectures for Data Access in a Shared Memory Hierarchy," J. Parallel and Distributed Computing, vol. 11, pp. 314-327, 1991.
[16] D.K. Panda and D. Basak, "Issues in Designing Scalable Systems with k-ary n-cube Cluster-c Organization," Proc. First Int'l Workshop Parallel Processing, India, pp. 5-10, 1994.
[17] D.A. Patterson, "Observations in Massive Parallelism—Trends and Predictions for 1995 to 2000," Technical Report 93-87, DIMACS, Sept. 1993.
[18] M.T. Raghunath, “Interconnection Network Design Based on Packaging Considerations,” PhD thesis, Computer Science Division, Univ. of California, Berkeley, 1993.
[19] M.T. Raghunath and A. Ranade, "Designing Interconnection Networks for Multi-Level Packaging," Proc. Supercomputing, pp. 772-781, 1993.
[20] E. Rothberg, J.P. Singh, and A. Gupta, "Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors," Proc. 20th Ann. Int'l Symp. Computer Architecture, pp. 14-25, ACM, May 1993.
[21] A.A. Sawchuk, C.S. Raghavandra, B.K. Jenkins, and A. Varma, “Optical Crossbar Networks,” IEEE Computer, vol. 20, no. 6, pp. 50–62, June 1987.
[22] S. L. Scott, J.R. Goodman, The Impact of Pipelined Channels on K-Ary N-Cube Networks IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 1, pp. 2-16, Jan. 1994.
[23] Principles of Electronic Packaging, Seraphim, Lasky, and Li, eds. McGraw Hill, 1989.
[24] Tummala and Rymaszewski, Microelectronics Packaging Handbook. Van Nostrand Reinhold, 1989.

Index Terms:
Multiprocessor systems, scalable systems, clustered architectures, hierarchical organization, k-ary n-cube interconnection, packaging constraints, parallel architectures, interconnection networks.
Citation:
Debashis Basak, Dhabaleswar K. Panda, "Designing Clustered Multiprocessor Systems under Packaging and Technological Advancements," IEEE Transactions on Parallel and Distributed Systems, vol. 7, no. 9, pp. 962-978, Sept. 1996, doi:10.1109/71.536940
Usage of this product signifies your acceptance of the Terms of Use.