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Issues in the Design of High Performance SIMD Architectures
August 1996 (vol. 7 no. 8)
pp. 818-829

Abstract—In this paper, we consider the design of high performance SIMD architectures. We examine three mechanisms by which the performance of this class of machines may be improved, and which have been largely unexplored by the SIMD community. The mechanisms are pipelined instruction broadcast, pipelining of the PE architecture, and the introduction of a novel memory hierarchy in the PE address space which we denote the direct only data cache, (dod-cache). For each of the performance improvements, we develop analytical models of the potential speedup, and apply those models to real program traces obtained on a MasPar MP-2 system. In addition, we consider the impact of all improvements taken together.

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Index Terms:
SIMD, pipelining, caches, MasPar, data parallel.
Citation:
James D. Allen, David E. Schimmel, "Issues in the Design of High Performance SIMD Architectures," IEEE Transactions on Parallel and Distributed Systems, vol. 7, no. 8, pp. 818-829, Aug. 1996, doi:10.1109/71.532113
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