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Packet Synchronization for Synchronous Optical Deflection-Routed Interconnection Networks
June 1996 (vol. 7 no. 6)
pp. 605-611

Abstract—Deflection routing resolves output port contention in packet-switched multiprocessor interconnection networks by granting the preferred port to the highest priority packet and directing contending packets out other ports. When combined with optical links and switches, deflection routing yields simple bufferless nodes, high-bit rates, scalable throughput, and low latency. We discuss the problem of packet synchronization in synchronous optical deflection networks with nodes distributed across boards, racks, and cabinets. Synchronous operation is feasible due to very predictable optical propagation delays. A routing control processor at each node examines arriving packets and assigns them to output ports. Packets arriving on different input ports must be bit-wise aligned; there are no elastic buffers to correct for mismatched arrivals. "Time-of-flight" packet synchronization is done by balancing link delays during network design. Using a directed graph network model, we formulate a constrained minimization problem for minimizing link delays subject to synchronization and packaging constraints. We demonstrate our method on a ShuffleNet graph, and show modifications to handle multiple packet sizes and latency-critical paths.

[1] W.D. Hillis and L.W. Tucker, “The CM-5 Connection Machine: A Scalable Supercomputer,” Comm. ACM, vol. 36, pp. 31–40, Nov. 1993.
[2] D. Gelernter, A. Nicolau, and D. Padua, Languages and Compilers for Parallel Computing, chap. "A Future-Based Parallel Language for a General-Purpose Highly-Parallel Computer." 1990.
[3] W. Oed, "CRAY T3D: Massively Parallel Processor System," Technical Report, Cray Research GmbH, ftp.cray.com /product-info/mpp/T3D_overview.ps, Nov. 1993.
[4] D. Lenoski et al., “The Stanford DASH Multiprocessor,” Computer, pp. 63-79, Mar. 1992.
[5] A. Agarwal et al., "The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor," Proc. Workshop on Scalable Shared Memory Multiprocessors, Kluwer Academic, 1991.
[6] E. Hagersten, A. Landin, and S. Haridi, "DDM—A Cache-Only Memory Architecture," Computer, Sept. 1992, pp. 44-54.
[7] P. Baran, "On Distributed Communication Networks," IEEE Trans. Comm. Systems, vol. 12, nos. 1-2, pp. 1-9, Mar. 1964.
[8] A. Ramanan, H. Jordan, J. Sauer, and D. Blumenthal, "An Extended Fiber-Optic Backplane for Multiprocessors," Proc. Hawaii Int'l Conf. System Sciences, 1993.
[9] A.G. Greenberg and B. Hajek, "Deflection Routing in Hypercube Networks," IEEE Trans. Comm., vol. 35, no. 6, pp. 1,070-1,081, June 1992.
[10] J. Midwinter, "Photonics in Switching: The Next 25 Years of Optical Communications?" IEE Proc., vol. 139, pp. 1-12, Feb. 1992.
[11] J. Feehrer, L. Ramfelt, and J. Sauer, "Design and Implementation of a Prototype Optical Deflection Network," Proc. Int'l Conf. Comm. Architectures, Protocols, and Applications, Aug.31- Sept.2 1994.
[12] G. Zorpette, "The Power of Parallelism," IEEE Spectrum, pp. 28-33, Sept. 1992.
[13] P.R. Prucnal, Photonics In Switching, Volume II, chap. "Photonic Fast Packet Switching." Academic Press, 1993.
[14] R. Nordin, Photonics in Switching, chap. 9. Academic Press, 1993.
[15] R. Khalil, "Clock Skew Analysis for Si and GaAs Receivers in Optical Clock Distribution Systems," vol. 1178, Optical Interconnects in the Computer Environment, pp. 171-176, SPIE, 1989.
[16] P.J. Delfyett, D.H. Hartman, and S.Z. Ahmed, "Optical Clock Distribution Using a Mode-Locked Semiconductor Laser Diode System," IEEE J. Lightwave Technology, vol. 9, pp. 1,646-1,649, Dec. 1991.
[17] D. Hartman, "Digital High Speed Interconnects: A Study of the Optical Alternative," Optical Eng., vol. 25, no. 25, pp. 1,086-1,102, 1986.
[18] I. Malitson, "Interspecimen Comparison of the Refractive Index of Fused Silica," J. Optical Soc. Am., vol. 55, pp. 1,205-1,209, Oct. 1965.
[19] A.L. Fisher and H.T. Kung,“Synchronising large VLSI processor arrays,” IEEE Trans. Computers, vol. 34, no. 8, pp. 734-740, Aug. 1984.
[20] D. Blumenthal, R. Feuerstein, and J. Sauer, "First Demonstration of Multihop All-Optical Packet Switching," IEEE Photonics Technology Letters, Mar. 1994.
[21] F. Borgonovo, L. Fratta, and F. Tonelli, "Circuit Service in Deflection Networks," Proc. IEEE INFOCOM, vol. 1, pp. 69-75, 1991.
[22] A. Krishna and B. Hajek,“Performance of shuffle-like switching networks with deflection,” Proc. IEEE INFOCOM’90, pp. 473-480, June, 1990.
[23] A. Acampora and S. Shah, "Multihop Lightwave Networks: A Comparison of Store-and-Forward and Hot-Potato Routing," IEEE Trans. Comm., vol. 40, no. 40, p. 1,082, 1992.
[24] J. Bannister, F. Borgonovo, L. Fratta, and M. Gerla, "A Versatile Model for Predicting the Performance of Deflection-Routing Networks," Performance Evaluation, vol. 16, pp. 201-221, 1992.
[25] F. Pittelli and D. Smitley, "Analysis of a 3D Toroidal Network for a Shared Memory Architecture," Proc. Supercomputing 88, pp. 42-47.
[26] K.E. Batcher, "Decomposition of Perfect Shuffle Networks," Proc. Int'l Conf. Parallel Processing, pp. I-255-I-262, 1991.
[27] H.F. Jordan, V.P. Heuring, and R. Feuerstein, "Optoelectronic Time-of-Flight Design and the Demonstration of an All-Optical, Stored Program, Digital Computer," Proc. IEEE Special Issue on Optical Computing, vol. 82, p. 1,678, Nov. 1994.
[28] P. Main, R. Feuerstein, V. Heuring, H. Jordan, J. Feehrer, and C. Love, "Implementation of a General Purpose Stored-Program Digital Optical Computer," Applied Optics, vol. 33, p. 1,619, Mar.10, 1994.
[29] M.G. Hluchyj and M.J. Karol, "ShuffleNet: An Application of Generalized Perfect Shuffles to Multihop Lightwave Networks," Proc. INFOCOM '88, pp. 379-380, 1988.
[30] J.R. Feehrer, L.H. Ramfelt, and D. Straub, "Implementation Details for Optical Deflection-Routed Multiprocessor Interconnect Prototype," technical report, Packet Network Laboratory Technical Report, Univ. of Colorado Optoelectronic Computing Systems Center, Mar. 1995.
[31] W.J. Dally and C.L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.
[32] C.E. Leiserson and J.B. Saxe, "Optimizing Synchronous Systems," J. VLSI and Computer Systems, vol. 1, no. 1, pp. 41-67, 1983.
[33] A. Gibbons, Algorithmic Graph Theory. Cambridge Univ. Press, 1985.
[34] N. Balabanian and T. Bickert, Electrical Network Theory. John Wiley&Sons, 1969.
[35] Cplex Optimization, Inc., Houston, TX., 1990.
[36] D.S. Johnson, C. Aragon, L. McGeoch, and C. Schevon, "Optimization by Simulated Annealing: An Experimental Evaluation, Part 1, Graph Partitioning," Operations Research, vol. 37, pp. 865-892, 1989.
[37] D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, Mass.: Addison-Wesley, 1989.
[38] J. Feehrer, L. Ramfelt, and J. Sauer, "An Optical Deflection-Routed Multiprocessor Interconnect," Proc. Sixth European Research Consortium for Informatics and Mathematics Workshop, pp. 103-115, June1-3, 1994.
[39] J.R. Feehrer, "Propagation Delay Uncertainty in Time-of-Flight Systems," PhD thesis, Electrical and Computer Eng. Dept., Univ. of Colorado Boulder, 1995.

Index Terms:
Deflection routing, interconnection networks, optical interconnects, packet switching, synchronization, integer programming, constrained optimization, propagation delay.
Citation:
John R. Feehrer, Lars H. Ramfelt, "Packet Synchronization for Synchronous Optical Deflection-Routed Interconnection Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 7, no. 6, pp. 605-611, June 1996, doi:10.1109/71.506699
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