
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Jean Frédéric Myoupo, Anne Cécile Fabret, "A Modular Systolic Linearization of the WarshallFloyd Algorithm," IEEE Transactions on Parallel and Distributed Systems, vol. 7, no. 5, pp. 449455, May, 1996.  
BibTex  x  
@article{ 10.1109/71.503769, author = {Jean Frédéric Myoupo and Anne Cécile Fabret}, title = {A Modular Systolic Linearization of the WarshallFloyd Algorithm}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {7}, number = {5}, issn = {10459219}, year = {1996}, pages = {449455}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.503769}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Parallel and Distributed Systems TI  A Modular Systolic Linearization of the WarshallFloyd Algorithm IS  5 SN  10459219 SP449 EP455 EPD  449455 A1  Jean Frédéric Myoupo, A1  Anne Cécile Fabret, PY  1996 KW  Modular linear systolic algorithms KW  transitive closure KW  shortest path KW  matrix multiplication. VL  7 JA  IEEE Transactions on Parallel and Distributed Systems ER   
Abstract—In this paper, we use a variant of the geometric method to derive efficient modular linear systolic algorithms for the transitive closure and shortest path problems. Furthermore, we show that partiallypipelined modular linear systolic algorithms with an output operation, for matrix multiplication, can be as fast as the fullypipelined existing ones and, moreover, they need less cells.
[1] A. Benaini and M. Tchuente, "Matrix Product on Linear Systolic Arrays," Parallel and Distributed Algorithms, M. Cosnard, P. Quinton, M. Raynal and Y. Robert, eds., NorthHolland, 1989.
[2] A.L. Fischer and H.T. Kung, "Synchronizing Large VLSI Processor Arrays," Proc. Tenth Ann. IEEE/ACM Symp. Computer Architecture, pp. 5458, June 1983.
[3] L.J. Guibas, H.T. Kung, and C.D. Thompson, "Direct VLSI Implementation of Combinatorial Algorithms, Proc. Conf. Very Large Scale Integration: Architecture, Design, Fabrication, pp. 509525, California Institute of Technology Inst., Jan. 1979.
[4] H.T. Kung, "Why Systolic Architecture," IEEE Computer, vol. 15, no. 1, pp. 3746, Jan. 1980.
[5] F.T. Leighton and C.E. Leiserson, WaferScale Integration of Systolic Arrays," Proc. 23rd Symp. Foundations of Computer Science, pp. 297311, Nov. 1982.
[6] S.Y. Kung,S.C. Lo,, and P.S. Lewis,“Optimal systolic design for the transitive closure and the shortest path problems,” IEEE Trans. Computers, vol. 36, pp. 603614, May 1987.
[7] P.Z. Lee and Z.M. Kedem,“Synthesizing linear array algorithms from nested for loop algorithms,” IEEE Trans. Computers, vol. 37, pp. 1,5781,598, Dec. 1988.
[8] P. Lee and Z. Kedem, "On High Speed Computing with a Programmable Linear Array Synthesizing Linear Array Algorithms From Nested For Loop Algorithms," J. Supercomputing. vol. 4, pp. 223249, 1990.
[9] D.I. Moldovan and J.A.B. Fortes, “Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays,” IEEE Trans. Computers, vol. 35, no. 1, pp.112, Jan. 1986.
[10] J.F. Myoupo, "A Linear Systolic Array for Transitive Closure Problems, Proc. Int'l Conf. Parallel Process. (ICPP), vol. 1, pp. 617618, 1990.
[11] J. F. Myoupo and A.C. Fabret, "Designing Modular Linear Systolic Arrays Using Dependence Graph Regular Partitions, Rapport Interne, L.R.I. N°760, UniversitéParis XI, 1992.
[12] V.K. Prasanna Kumar and Y.C. Tsai, "Designing Linear Systolic Arrays, J. Parallel Distributed Computers, vol. 7, pp. 441463, 1989.
[13] S.K. Prasanna Kumar and Y.C. Tsai, "On Mapping Algorithms to Linear and FaultTolerant Systolic Arrays," IEEE Trans. Computers, vol. 38, no. 3, pp. 470478, 1989.
[14] I.V. Ramakrishnan, P.J. Varman, "Dynamic Programming and Transitive Closure on Linear Pipelines," Proc. Int'l. Conf. on Parallel Processing, (ICPP) 1984.
[15] I.V. Ramakrishnan, D.S. Fussel, and A. Silberschatz, "Mapping Homogenous Graphs on Linear Arrays," IEEE Trans. Computers, vol. 35, pp. 189209, 1986.
[16] P.J. Varman and I.V. Ramakrishnan, "Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays," IEEE Trans. Computers, vol. 35, no. 11, pp. 989996, Nov. 1986.
[17] T. Risset, "Linear Systolic Arrays for Matrix Multiplication: Comparison of Existing Synthesis Methods and New Results," Algorithms and Parallel VLSI Architectures II, pp. 163174, P. Quinton and Y. Robert eds. NorthHolland: Elsevier, 1991.
[18] G. Rote, "A Systolic Array Algorithm for the Algebraic Path Problem," Computing, vol. 34, pp. 192219, 1985.
[19] W. Shang and J.A.B. Fortes, "On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays," IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 5, pp. 350363, May 1992.
[20] U. Schwiegelshohn and L. Thiele, "Linear Systolic Arrays for Matrix Computation," J. Parallel Distributed Computers, vol. 7, pp. 2839, 1989.
[21] J. Teich and L. Thiele, "A Transformative Approach to the Partitioning of Processor Arrays," Proc. ASAP 1992, IEEE C. S. Press, pp. 420.
[22] J.D. Ullman, Computational aspects of VLSI, IEEE C. S. Press, 1984.
[23] J.L.A. Van de Snepscheut, "A Derivation of a Distributed Implementation of Warshall's Algorithm," Science of Computer Programming, vol. 7, pp. 5560, 1986.
[24] S.W. Warman Jr., "A Modification of Warshall's Algorithm for the Transitive Closure of Binary Relations," CACM, vol. 18, no. 4, pp. 218220, 1975.
[25] S. Warshall, "A Theorem on Boolean Matrices," J. ACM, vol. 9 no. 1, pp. 1112, 1972.