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Issue No.03 - March (1996 vol.7)
pp: 274-287
<p><b>Abstract</b>—Processor arrays are frequently used to deliver high performance in many applications with computationally intensive operations. This paper presents the <it>General Parameter Method</it> (<it>GPM</it>), a systematic parameter-based approach for synthesizing such algorithm-specific architectures. GPM can synthesize <it>processor arrays of any lower dimension</it> from a <it>uniform-recurrence description</it> of the algorithm. The design objective is a general <it>nonlinear and nonmonotonic user-specified function</it>, and depends on attributes such as computation time of the recurrence on the processor array, completion time, load time, and drain time. In addition, bounds on some or all of these attributes can be specified. GPM performs an efficient search of <it>polynomial complexity</it> to find the <it>optimal</it> design satisfying the user-specified design constraints. As an illustration, we show how GPM can be used to find optimal linear processor arrays for computing transitive closures. We consider design objectives that minimize computation time, or processor count, or completion time (including load and drain times), and user-specified constraints on number of processing elements and/or computation/completion times. We show that GPM can be used to obtain optimal designs that trade between number of processing elements and completion time, thereby allowing the designer to choose a design that best meets the specified design objectives. We also show the equivalence between the model assumed in GPM and that in the popular dependence-based methods [<ref rid="bibl02741" type="bib">1</ref>], [<ref rid="bibl02742" type="bib">2</ref>]. Consequently, GPM can be used to find optimal designs for both models.</p>
Design constraints, objective function, optimal design, polynomial-time search, processor arrays, transitive closure, uniform recurrence equations.
Kumar N. Ganapathy, Benjamin W. Wah, "Optimal Synthesis of Algorithm-Specific Lower-Dimensional Processor Arrays", IEEE Transactions on Parallel & Distributed Systems, vol.7, no. 3, pp. 274-287, March 1996, doi:10.1109/71.491581
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