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Performance Analysis of Finite-Buffered Asynchronous Multistage Interconnection Networks
January 1996 (vol. 7 no. 1)
pp. 18-25

Abstract—In this paper, we present a queueing model for performance analysis of finite-buffered multistage interconnection networks. The proposed model captures network behavior in an asynchronous communication mode and is based on realistic assumptions. A uniform traffic model is developed first and then extended to capture nonuniform traffic in the presence of hot-spot. Throughput and delay are computed using the proposed model and the results are validated via simulation. The analysis is extended to predict performance of MIN-based multiprocessors. The effects of buffer length, switch size, and the maximum allowable outstanding requests on the system performance are discussed. Various design decisions using this model are drawn with respect to delay, throughput, and system power.

[1] J. Konicek,T. Tilton et al, "The organization of the Cedar system," Proc. Int'l Conf. Parallel Processing, pp. 49-56, Aug. 1991.
[2] A. Gottlieb,R. Grishman et al., "The NYU Ultracomputer-Designing a MIMD shared memory parallel computer," IEEE Trans. Computers, pp. 175-189, Feb. 1983.
[3] G.F. Pfister,W.C. Brantly et al., , "The IBM research parallel processor prototype (RP3) : Introduction and architecture," Proc. Int'l Conf. Parallel Processing, pp. 764-771, Aug. 1985.
[4] H.J. Siegel,L.J. Siegel et al., , "PASM: A partitionable SIMD/MIMD system for image processing and pattern recognition," IEEE Trans. Computers, vol. 30, pp. 934-947, Dec. 1981.
[5] C. Wu and M. Lee,"Performance Analysis of Multistage Interconnection Network Configurations and Operations," IEEE Trans. Computers, vol. 41, no. 1, pp. 18-27, Jan. 1992.
[6] H. Jiang, L.N. Bhuyan, and J.K. Muppala, "MVAMIN: Mean Value Analysis Algorithms for Multistage Interconnection Networks," J. Parallel and Distributed Computing, vol. 12, no. 3, pp. 189-201, July 1991.
[7] D.M. Dias and J.R. Jump,"Analysis and simulation of buffered delta network," IEEE Trans. on Computers, pp. 273-282, Aug. 1981.
[8] D. Willick and D. Eager, “An Analytical Model of Multistage Interconnection Networks,” Proc. ACM SIGMETRICS, pp. 192-202, May 1990.
[9] A. Merchant,"A Markov chain approximation for the analysis of Banyan networks," Proc. ACM SIGMETRICS Conf. Measurement and Modeling of Computer Systems, pp. 60-67, May 1991.
[10] T. Liu and L Kleinrock,“Performance analysis of finite-buffered multistage interconnection networks with a general traffic pattern,”in1991 ACM SIGMETRICS Conf.,San Diego, CA, May 1991, pp. 68–78.
[11] Y.-C. Jenq,"Performance analysis of a packet switch based on a single-buffered Banyan network," IEEE J. Selected Areas Comm., vol. 1, pp.1,014-1,021, Dec. 1983.
[12] H. Yoon,K.Y. Lee,, and M.T. Liu,“Performance analysis of multibuffered packet-switching networks in multiprocessor systems,” IEEE Trans. Computers, vol. 39, no. 3, pp. 319-327, Mar. 1990.
[13] J. Ding and L.N. Bhuyan,"Performance evaluation of multistage interconnection networks with finite buffers," Int'l Conf. Parallel Processing, pp. 592-599, Aug. 1991.
[14] T.N. Mudge and B.A. Makrucki,"An approximate queueing model for packet switched multistage interconnection networks," Proc. Int'l Conf. Distributed Computing Systems, pp. 556-562, Oct. 1982.
[15] G.F. Pfister and V.A. Norton,"Hot spot contention and combining in multistage interconnection networks," Proc. Int'l Conf. Parallel Processing, pp. 790-797, 1985.
[16] P.-C. Yew,N.-F. Tzeng, and D.H. Lawrie,"Distributing hot-spot addressing in large-scale multiprocessors," Int'l Conf. Parallel Processing, pp. 51-58, Aug. 1986.
[17] G. Lee,“A performance bound of multistage combining networks,”IEEE Trans. Comput., vol. 38, pp. 1387–1395, Oct. 1989.
[18] S.R. Dickey and O.E. Percus,"Performance differences among combining switch architectures," Proc. Int'l Conf. on Parallel Processing, vol. 1, pp. 110-117, Aug. 1992.
[19] R. Jain,The Art of Computer Systems Performance Analysis. John Wiley&Sons, New York 1991.
[20] B.V. Gnedenko and I.N. Kovalenko,Introduction to Queueing Theory, Second Edition. Boston: Birkhauser, 1989.
[21] Y. Mun and H.Y. Youn,“Performance analysis of finite buffered multistage interconnection networks,” IEEE Trans. Computers, vol. 43, no. 2, pp. 153-162, Feb. 1994.

Index Terms:
Multiprocessor, multistage interconnection network, finite buffer, performance analysis, queueing model.
Prasant Mohapatra, Chita R. Das, "Performance Analysis of Finite-Buffered Asynchronous Multistage Interconnection Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 7, no. 1, pp. 18-25, Jan. 1996, doi:10.1109/71.481594
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