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Routing in Modular Fault-Tolerant Multiprocessor Systems
November 1995 (vol. 6 no. 11)
pp. 1206-1220

Abstract—In this paper, we consider a class of modular multiprocessor architectures in which spares are added to each module to cover for faulty nodes within that module, thus forming a fault-tolerant basic block (FTBB). In contrast to reconfiguration techniques that preserve the physical adjacency between active nodes in the system, our goal is to preserve the logical adjacency between active nodes by means of a routing algorithm which delivers messages successfully to their destinations. We introduce two-phase routing strategies that route messages first to their destination FTBB, and then to the destination nodes within the destination FTBB. Such a strategy may be applied to a variety of architectures including binary hypercubes and three-dimensional tori. In the presence of f faults in hypercubes and tori, we show that the worst case length of the message route is min {σ+f, (K+ 1)σ};+c where σ is the shortest path in the absence of faults, K is the number of spare nodes in an FTBB, and c is a small constant. The average routing overhead is much lower than the worst case overhead.

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Index Terms:
Sparing, modular multiprocessors, fault-tolerant routing, hypercube multicomputers, mesh connected processors.
Citation:
M. Sultan Alam, Rami G. Melhem, "Routing in Modular Fault-Tolerant Multiprocessor Systems," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 11, pp. 1206-1220, Nov. 1995, doi:10.1109/71.476192
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