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An Asynchronous Distributed Approach for the Simulation of Behavior-Level Models on Parallel Processors
June 1995 (vol. 6 no. 6)
pp. 639-652

Abstract—Traditional approaches to the distributed simulation of digital designs are limited in that they are inefficient and prone to deadlock for systems with feedback loops. This paper proposes an asynchronous distributed algorithm to the simulation and verification of behavior-level models and describes its implementation on an actual loosely-coupled parallel processor. The approach is relatively efficient for realistic digital designs and mathematically shown to be deadlock free. Additionally, it includes a new technique [6] for modeling the timing of digital systems that guarantees the accuracy of the simulation results. In the discipline of computer-aided design of digital systems, a behavior model refers to a compact and executable representation of the activities of a complex digital component or an entire digital system such as the Motorola 68000, expressed through a high-level hardware description language such as ADLIB [2] or VHDL [1]. Behavior models are popular because of their flexibility; however, they execute excruciatingly slow on uniprocessor computers. The approach presented in this paper has the potential to significantly reduce the execution time through concurrent execution on multiple processors. In this approach, a design is first partitioned by the user and the behavior models corresponding to the digital components of each partition are assigned to a unique processor of the parallel processor system. In course of execution, a behavior model receives signal transitions from other models through the explicit communication links, termed protocols, that model the connectivity of the digital design. Every model is completely unaware of the existence of other entities in the simulation system and is solely responsible for accurately scheduling its execution on the underlying processor. Thus, scheduling is distributed in the models and the approach, like the Chandy–Misra algorithm [11], does not require any knowledge of the global simulation time. However, this paper differs from [11] in that 1) it redefines the notion of deadlock in nonfeedback systems [11] as starvation and proposes a new methodology to address it, and 2) introduces a new mode—“exception-mode”, of execution to prevent the occurrence of deadlock in feedback systems. This paper also reports on an implementation of the approach on the 64 node Bell Labs hypercube [3], [4] and the ARMSTRONG [24] system at Brown University. Performance statistics based on the simulation of several representative designs indicate that the approach achieves significant speedup for realistic combinational behavior-level digital systems while the speedup for sequential designs is a function of the system and other factors.

Index Terms—Distributed simulation, digital systems simulation, asynchronous algorithms, parallel processors.

[1] VHDL Language Reference Manual, IEEE Standard 1076, 1989.
[2] D. Hill,ADLIB Users Manual.Comput. Syst. Lab., Stanford Univ., CA, Tech. Rep. 177, 1979.
[3] C. L. Seitz,“The cosmic cube,”CACM, vol. 28, pp. 22–33, Jan. 1985.
[4] E. DeBenedictis,“Multiprocessor programming with distributed variables,”inProc. Conf. Hypercube Multiprocessor, Aug. 1985.
[5] D. C. Luckham, A. Stanculescu, Y. Huh, and S. Ghosh,“The semantics of timing constructs in hardware description languages,”inProc. Int. Conf. Comput. Design, pp. 10–14, Oct. 1986.
[6] S. Ghosh and M. Yu,“A preemptive scheduling mechanism for accurate behavioral simulation of digital designs,”IEEE Trans. Comput., vol. 38, Nov. 1989.
[7] B. Stroustrup, The C++ Programming Language. Addison-Wesley, 1986.
[8] M. M. Denneau,“The Yorktown simulation engine,”inProc. 19th ACM/IEEE DA Conf., 1983, pp. 55–59.
[9] J. K. Howardet al.,“Introduction to the IBM Los Gatos logic simulation engine,”inProc. ICCD, Oct. 1983, pp. 580–583.
[10] The ZYCAD Logic Evaluator: Product Description,ZYCAD Corp., N. Roseville, MN, 1983.
[11] J. Misra, "Distributed Discrete-Event Simulation," ACM Computing Surveys, vol. 18, no. 1, pp. 39-65, Mar. 1986.
[12] K.M. Chandy, J. Misra, and L. Hass, "Distributed Deadlock," ACM Trans. Computer Systems, vol. 1, no. 2, pp. 144-156, May 1983.
[13] L. Lamport, "Time, clocks and the ordering of events in a distributed system," Comm. ACM, vol. 21, no. 7, pp. 558-565, July 1978.
[14] J. K. Peacocket al.,“Distributed simulation using a network of processors,”Comput. Networks, vol. 3, no. 1, pp. 44–56, 1979.
[15] Daisy Megalogician: Product description,Daisy Syst., Mountain View, 1984.
[16] M. E. Glazieret al.,“ULTIMATE: A hardware logic simulation engine,”inProc. 20th ACM/IEEE DA Conf., 1984, pp. 336–342.
[17] M. Bloom,“Behavior models take the pain out of system simulation,”Comput. Design, pp. 38–46, Feb. 15, 1987.
[18] D.R. Jefferson, "Virtual Time," ACM Trans. Programming Languages and Systems, vol. 7, no. 3, pp. 404-425, July 1985.
[19] S. Ghosh and M.-L. Yu,“An asynchronous distributed approach for the simulation of behavior-level models on parallel processors,”inProc. 1988 Int. Conf. Parallel Processing, St. Charles, IL, Aug. 15–19, 1988.
[20] K.M. Chandy and J. Misra, “Asynchronous Distributed Simulation via a Sequence of Parallel Computations,” Comm. ACM, vol. 24, no. 11, pp. 198–206, Aug. 1981.
[21] D. A. Reed and A. Malony,“Parallel discrete event simulation: The Chandy-Misra approach,”inProc. SCS Multiconf. Distrib. Simulation, San Diego, CA, Feb. 3–5, 1988, pp. 8–13.
[22] Private communications with K. F. Wong, Dep. Comput. Sci., Washington Univ., St. Louis, MO, June 1988.
[23] Private communication with Prof. E. Cerny, Dep. Comput. Sci., Univ. Montreal, Montreal, PQ, Canada, Apr. 1991.
[24] J. T. Rayfield and H. F. Silverman,“Operating system and applications of the Armstrong multiprocessor,”IEEE Comput., vol. 21, pp. 38–52, June 1988.
[25] P. Agrawal, W. Dally, A. Ezzat, W. Fischer, H. Jagadish, and A. Krishnakumar,“Architecture and design of the MARS hardware accelerator,”inProc. 24th Design Automation Conf., Miami Beach, FL, June 1987, pp. 101–107.
[26] S. Ghosh,“Ada as a hardware description language,”IEEE Design and Test Comput., Feb. 1988.
[27] M. Barbacci, D. P. Siewiorek, R. Gordon, R. Howbrigg, and S. Zuckerman,“An architectural research facility—ISP descriptions, simulation, and data collection,”inProc. Nat. Comput. Conf., vol. 46, 1977.
[28] R. DeVries,“Reducing null messages in Misra's distributed discrete event simulation method,”IEEE Trans. Software Eng., vol. 16, pp. 82–91, Jan. 1990.
[29] H.-C. Shih, P. G. Kovijanic, and R. Razdan“A global feedback detection algorithm for VLSI circuits,”inProc. ICCD, Boston, MA, Sept. 17, 1990, pp. 37–40.
[30] S. Davidson and J. Lewandowski,“ESIM/AFS—A concurrent architectural level fault simulator,”inProc. Int. Test Conf., Washington DC, Oct. 1986, pp. 375–383.
[31] P. M. Athanas and H. F. Silverman,“The reconfigurable communications architecture of the ARMSTRONG II processor,”Div. Eng., Brown Univ., Providence, RI, LEMS Tech. Rep. 83, Apr. 1991,
[32] N. Deo,Graph Theory with Applications to Engineering and Computer Science.Englewood Cliffs, NJ: Prentice–Hall, 1974.
[33] E.G. Ulrich,“Exclusive simulation of activity in digital networks,” Comm. ACM, vol. 12, no. 2, pp. 102-110, 1969.
[34] J. Sissler,“Assessing the potential of multi-threaded VHDL simulation,”inVHDL Boot Camp Proc., Fall '93 Conf., San Jose, CA, Oct. 10–13, 1993, pp. 131–136.
[35] P. Chawla, H. Carter, D. Barker, and S. Bilik,“Preliminary design and analysis of a hardware accelerator for VHDL simulation,”inVHDL Boot Camp Proc., Fall '93 Conf., San Jose, CA, Oct. 10–13, 1993, pp. 267–279.
[36] P. J. Ashden, H. Detmold and W. S. McKeen,“Parallel execution of VHDL models,”Dep. Comput. Sci., Univ. Adelaide, Australia, Tech. Rep. 93-01.
[37] M. L. Bailey,“A time-based model for investigating parallel logic-level simulation,”IEEE Trans. Comput.-Aided Design, vol. 11, pp. 816–824, July 1992.
[38] F. Mattern, “Efficient Algorithms for Distributed Snapshots and Global Virtual Time Approximation,” J. Parallel and Distributed Computing, vol. 18, no. 4, pp. 423-434, Aug. 1993.
[39] I.F. Akyildiz, L. Chen, S.R. Das, R. Fujimoto, and R. Serfozo, “The Effect of Memory Capacity on Time Warp Performance,” J. Parallel and Distributed Computing, vol. 18, no. 4, pp. 411-422, 1993.
[40] D.M. Nicol and P. Heidelberger, “Optimistic Parallel Simulation of Continuous Time Markov Chains Using Uniformization,” J. Parallel and Distributed Computing, vol. 18, no. 4, pp. 395-410, 1993.
[41] T.K. Som and R.G. Sargent, “A New Process to Processor Assignment Criterion for Reducing Rollbacks in Optimistic Simulation,” J. Parallel and Distributed Computing, vol. 18, no. 4, pp. 509-515, 1993.
[42] C.-P. Wen and K. A. Yelick,“Parallel timing simulation on a distributed memory multiprocessor,”inProc. ICCAD, Santa Clara, CA, Nov. 7–11, 1993, pp. 131–136.
[43] J.V. Briner, J.L. Ellis, and G. Kedem, “Breaking the Barrier of Parallel Simulation of Digital Systems,” Proc. 28th Design Automation Conf., June 1991.
[44] J. S. Steinman,“SPEEDES: Synchronous parallel environment for emulation and discrete event simulation,”inProc. Fifth Workshop Parallel and Distrib. Simulation (PADS '91), Anaheim, CA, 1991, pp. 95–103 (the Society for Computer Simulation, San Diego, CA).
[45] K. M. Chandy and R. Sherman,“The conditional event approach to distributed simulation,”SCS Multiconf. Distrib. Simulation, Tampa, FL, Mar. 28–31, 1989, pp. 93–99.
[46] D. West,“Lazy rollback and lazy reevaluation,”M.S. thesis, Univ. Calgary, Jan. 1988.
[47] R. Fujimoto, “Parallel Discrete Event Simulation,” Comm. ACM, vol. 33, no. 10, pp. 30-53, Oct. 1990.
[48] L. Soule and T. Blank, “Parallel Logic Simulation on General PurposeMachines,” Proc. 26th Design Automation Conf., pp. 81-86, June 1989.
[49] L. Soule and T. Blank,“Parallel logic simulation on general purpose machines,”inProc. 25th Design Automat. Conf., June 1988.

Sumit Ghosh, Meng-Lin Yu, "An Asynchronous Distributed Approach for the Simulation of Behavior-Level Models on Parallel Processors," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 6, pp. 639-652, June 1995, doi:10.1109/71.388044
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