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Issue No.05 - May (1995 vol.6)
pp: 554-560
ABSTRACT
<p><it>Abstract—</it>A cross-bridge reconfigurable array of processors is a parallel processing system which has the ability to change dynamically the supported interconnection scheme during the execution of an algorithm. Based on this architecture, several <math><tmath>$O(1)$</tmath></math> time basic operations such as the transpose, the untranspose, the shift, the unshift and the prefix sum of a binary sequence are first proposed. Then, these basic operations can be used to find the <math><tmath>$k$</tmath></math>th smallest element of <math><tmath>$N$</tmath></math><math><tmath>$m$</tmath></math> bits unsigned integers in <math><tmath>$O(m)$</tmath></math> time using <math><tmath>$N$</tmath></math> processors and to sort <math><tmath>$N$</tmath></math> data items in <math><tmath>$O(1)$</tmath></math> time using <math><tmath>$O(N^{{5}\over{3}})$</tmath></math> processors instead of using <math><tmath>$O(N^2)$</tmath></math> processors as those proposed by other researchers [<ref type="bib" rid="D05542">2</ref>], [<ref type="bib" rid="D05544">4</ref>], [<ref type="bib" rid="D05548">8</ref>], [<ref type="bib" rid="D055412">12</ref>], [<ref type="bib" rid="D055417">17</ref>], respectively.</p><p><it>Index Terms—</it>Prefix sum, selection, sort, parallel algorithms, cross-bridge, reconfigurable bus, reconfigurable array of processors.</p>
CITATION
Tzong-Wann Kao, Shi-Jinn Horng, Yue-Li Wang, Horng-Ren Tsai, "Designing Efficient Parallel Algorithms on CRAP", IEEE Transactions on Parallel & Distributed Systems, vol.6, no. 5, pp. 554-560, May 1995, doi:10.1109/71.382325
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