This Article 
 Bibliographic References 
 Add to: 
Properties of Generalized Branch and Combine Clock Networks
May 1995 (vol. 6 no. 5)
pp. 541-546

Abstract—In a recent development a new clock distribution scheme has been introduced. The scheme called Branch-and-Combine or BaC, is the first to guarantee constant skew bound regardless of network size. In this paper we generalize and extend the work on BaC networks. Our study takes the approach of defining a general graph theoretic model which is then utilized to define a general network model taking into account node function. We use the models to establish some interesting results on clocking paths, node input sequences, node inputs' relative timings, and skew bound. We prove that a network adhering to our general model is stable (will not oscillate) despite its cyclic nature. We also prove that no tree of any kind can be used to distribute the clock in two or more dimensions such that skew bound is constant. The paper then exploits the derived properties to describe the inherent interplay between topology, timing, node function, and skew bound.

Index Terms—Branch-and-combine network, clock distribution, skew bound, synchronous system, VLSI, large system, network stability, cyclic clock networks.

[1] M. Alghahi and C. Svensoon,"Performance of Synchronous and Asynchronous Schemes for VLSI Systems," IEEE Trans. Computers, vol. 41, no. 7, pp. 838-872, July 1992.
[2] M. D. Dikaiakos and K. Steiglitz,“Comparison of tree and straight-line clocking for long systolic arrays,”inASSP Conf., vol. 3.4, Aug. 1984, pp. 1177–1180.
[3] A. El-Amawy,“Branch-and-combine clocking of arbitrarily large computing networks,”inProc. Int. Conf. Parallel Process., St. Charles, IL, Aug. 1991, pp. I-409–I-417.
[4] ——,“Arbitrarily large clock networks with constant skew bound,”U.S. Patent S,163,068, 1992.
[5] ——,“Clocking arbitrarily large computing structures under a constant skew bound,”IEEE Trans. Parallel Distrib. Syst., vol. 4, no. 3, pp. 241–255, Mar. 1993.
[6] A. El-Amawy and U. Maheshwar,“A comparative study of synchronous clocking schemes for VLSI,”J. VLSI Des., in print.
[7] A.L. Fisher and H.T. Kung,“Synchronising large VLSI processor arrays,” IEEE Trans. Computers, vol. 34, no. 8, pp. 734-740, Aug. 1984.
[8] J. P. Fishburn,“Clocking skew optimization,”IEEE Trans. Comput., vol. 39, pp. 945–951, July 1990.
[9] R. Gould,Graph Theory. Menlo Park, CA: Benjamin Cummings, 1988.
[10] S. Kugelmass and K. Steiglitz,“An upper bound on expected clock skew in sychronous systems,”IEEE Trans. Comput., vol. 39, no. 12, pp. 1475–1477, Dec. 1990.
[11] S.-Y. Kung and R. J. Gal-Ezer,“Synchronous versus asynchronous computation in VLSI array processors,”inProc. SPIE, May 1982, vol. 341, pp. 53–65.
[12] C. L. Seitz,“Systems timings,”C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, ch. 7.
[13] D. Wann and M. Franklin,“Asynchronous and clocked control structures for VLSI based interconnection networks,”IEEE Trans. Comput., vol. C-32, no. 3, pp 284–293, Mar. 1983.
[14] K. D. Wagner,“Clock system design,”IEEE Des., Test., Comput., pp. 9–22, Oct. 1988.

Ahmed El-Amawy, Priyalal Kulasinghe, "Properties of Generalized Branch and Combine Clock Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 5, pp. 541-546, May 1995, doi:10.1109/71.382323
Usage of this product signifies your acceptance of the Terms of Use.