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An Interface to a Reliable Packet Delivery Service for Parallel Systems
April 1995 (vol. 6 no. 4)
pp. 400-411

Abstract—Modern distributed memory parallel computers provide hardware support for the efficient and reliable delivery of interprocessor messages. This facility needs to be accessed by lightweight protocols that do not waste the performance of the underlying hardware; the heavyweight layering techniques traditionally used in distributed systems are wholly inappropriate. A low-level communication interface is therefore presented which exploits modern architectures effectively, while maintaining a good match to existing parallel programming environments. The interface defines mechanisms to access an asynchronous reliable packet delivery service. It permits messaging protocols to be efficiently synthesized by considering the activity at their end-points alone. This arrangement effectively decouples the implementation of protocols from low-level architectural features, and hence aids the portability of parallel programming environments. Furthermore, the interface allows the communication network to be shared by multiple programming paradigms, giving additional flexibility over existing systems.

Index Terms—Communication networks, multicomputers, packet routing, parallel processing, protocol support, standard interface.

[1] G. Fox,M. Johnson,G. Lyzenga,S. Otto,J. Salmon,, and D. Walker,Solving Problems on Concurrent Processors, Vol. I: General Techniques andRegular Problems.Englewood Cliffs, N.J.: Prentice Hall 1988.
[2] G. C. Fox,“Parallel computing comes of age: Supercomputer level parallel computations at Caltech,”Concurrency: Practice and Experience, vol. 1, pp. 63–103, Sept. 1989.
[3] C. L. Seitz and J. Matisoo,“Engineering limits on computer performance,”Physics Today, pp. 38–45, 1984.
[4] G. C. Fox and D. Walker,“Concurrent supercomputers in science,”inProc. Conf. Comput. Physics Instruct., Aug. 1988.
[5] M. Kallstrom and S. S. Thakkar,“Programming three parallel computers,”IEEE Software Mag., vol. 5, pp. 11–22, Jan. 1988.
[6] DRAFT High Performance Fortran Language Specification, High Performance Fortran Forum, Jan. 1993.
[7] Express Transputer Logical System C Manual, Parasoft Corp., Pasadena, CA, 1990.
[8] iPSC/2 and iPSC/860 User's Guide, Intel Corp., 1990.
[9] Meiko, Bristol, UK,CS-Tools for SunOS, 1990.
[10] R. Hempel,“The Argonne/GMD macros in Fortran for portable parallel programming using the message passing programming model,”St. Augustin 1, West Germany, Tech. Rep., GMD, 5205, Apr. 1991.
[11] J. J. Dongarra, R. Hempel, A. J. G. Hey, and D. W. Walker,“A proposal for a user-level, message passing interface in a distributed memory environment,”Oak Ridge Nat. Lab., Tech. Rep. TM-12231, Mar. 1993.
[12] C. L. Seitz,“The cosmic cube,”CACM, vol. 28, pp. 22–33, Jan. 1985.
[13] D. M. Pase and A. R. Larrabee,“Intel iPSC concurrent computer,”inProgramming Parallel Processors. Reading, MA: Addison-Wesley, 1988, pp. 105–124.
[14] J.P. Hayes et al., “A Microprocessor-Based Hypercube Supercomputer,” IEEE Micro, Vol. 6 No. 5 Oct. 1986, pp. 6–17.
[15] The Transputer Databook, Inmos Ltd., Bristol, UK, 1989.
[16] D. A. Nicole,“ESPRIT P1085, a reconfigurable transputer processor architecture,”inCONPAR 88, Cambridge Univ. Press for British Comput. Soc. 1989.
[17] TMS320C4X User's Guide, Texas Instruments, 1991.
[18] W.J. Dally and C.L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.
[19] L. M. Ni and P. McKinley,“A survey of wormhole routing techniques in direct networks,”IEEE Comput., 26(2):62–76, Feb., 1993.
[20] S. Nugent, "The iPSC/2 Direct-Connect Communications Technology," Proc. Third Conf. Hypercube Concurrent Computers and Applications, pp. 51-60, Jan. 1998.
[21] Touchstone DELTA System Description, Intel Supercomputer Syst. Div., Intel Corp., Beaverton, OR, Feb. 1991, advanced information.
[22] H. Ishihata, T. Horie, S. Inano, T. Shimizu, and S. Kato,“An architecture of highly parallel computer AP1000,”inProc. IEEE Pacific Rim Conf. Commun., Comput. Sign. Process., May 1991.
[23] CS-2, Meiko, product description, 1992.
[24] IBM solutions: Scalable POWERparallel system 1,IBM, IBM Tech. Comput. Group, product description, 1993.
[25] The T9000 Transputer Hardware Reference Manual, Inmos Ltd., Bristol, UK, 1993.
[26] E. Hagersten, A. Landin, and S. Haridi,“DDM—A cache-only memory architecture,”IEEE Comput. Mag., vol. 25, pp. 44–54, Sept. 1992.
[27] L. Curran,“Kendall Square banks on its technology,”Electron., vol. 65, pp. 20–21, Feb. 1992.
[28] M. Debbage, M. B. Hill, and D. A. Nicole,“Global communications on locally-connected message-passing parallel computers,”Concurrency: Practice and Experience, vol. 5, pp. 491–509, Sept. 1993.
[29] M. Debbage,“Reliable Communication Protocols for High Performance Computing,”Ph.D. dissertation, Univ. Southampton, 1993.
[30] L. Clarke and G. Wilson, “Tiny: An Efficient Routing Harness for the Inmos Transputer,” Concurrency: Practice and Experience, Vol. 3, No. 3, June 1991, pp. 221–245.
[31] H. Oakley,“Mercury: An operating system for medium-grained parallelism,”Microprocess. Microsyst., vol. 13, pp. 97–102, Mar. 1989.
[32] L. Kleinrock,“ARPANET lessons,”inInt. Con. Commun., June 1976.
[33] M. Debbage, M. B. Hill, and D. A. Nicole,“A general purpose parallel programming environment,”inProc. World OCCAM Transputer User Group 14th Tech. Meeting, Sept. 1991, pp. 123–132.
[34] Virtual Channel Router version 2.0 user guide, ESPRIT Project PUMA P2701 working paper 25, Univ. Southampton, June 1991.
[35] OCCAM 2Reference Manual, Inmos Ltd., Bristol, UK, 1988.
[36] I. Glendinning, V. S. Getov, S. A. Hellberg, R. W. Hockney, and D. J. Pritchard,“Performance visualization in a portable parallel programming environment,”inWorkshop Perform. Measure. Visualization Parallel Syst., 1992.
[37] A. G. Smith,“CHIMP-UPR design,”Edinburgh Parallel Comput. Ctr., Tech. Note EPCC-KTP-CHIMP-DESIGN-UPR 1.0, 1992.
[38] G. Barrett, E. Barton, T. Carden, D. Duval, and D. Nicole,“General purpose parallel computers,”inProc. World OCCAM Transputer User Group 15th Tech. Meeting, Apr. 1992.
[39] A. D. Culloch,“Porting the 3L parallel C environment to the Texas Instruments TMS320C40,”inProc. World OCCAM Transputer User Group 15th Tech. Meeting, Apr. 1992.
[40] PACT Parallel C/Transputer Compiler Reference Manual Version 1.0, PACT, Foulkeslaan 87, 2625RB Delft, The Netherlands, Feb. 1992.

Citation:
Mark Debbage, Mark B. Hill, and Denis A. Nicole, "An Interface to a Reliable Packet Delivery Service for Parallel Systems," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 4, pp. 400-411, April 1995, doi:10.1109/71.372793
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