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Issue No.03 - March (1995 vol.6)
pp: 303-313
<p><it>Abstract—</it>Performance in superscalar processing strongly depends on the compiler's ability to generate codes that can be executed by hardware in an optimal or near optimal order. Generating optimal code is an NP-complete problem. However, there is a need for highly optimized code, such as in superscalar or real-time systems. In this paper, an instruction scheduling scheme for optimizing a program trace is proposed. Optimized code can be arrived at without much redundant work, if some important features in code are well explored and utilized in scheduling. To formalize the task, two abstract models, one for a superscalar processor and the other for a program trace, are given. These two models reflect most of the characteristics of the scheduling problem. The interrelations between instructions and partial schedules are thoroughly studied, and dominance and equivalence relations on them are defined. These relations are then used to reduce the solution space and eventually help to produce optimal schedules. The results of experiments that show the promise of the proposed scheme are also presented.</p><p><it>Index Terms—</it>Pipeline processors, sequencing and scheduling, optimization, prune and search, and NP-completeness.</p>
Hong-Chich Chou, "An Optimal Instruction Scheduler for Superscalar Processor", IEEE Transactions on Parallel & Distributed Systems, vol.6, no. 3, pp. 303-313, March 1995, doi:10.1109/71.372778
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