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| Mu-Cheng Wang, Howard Jay Siegel, Mark A. Nichols, Seth Abraham, "Using a Multipath Network for Reducing the Effects of Hot Spots," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 3, pp. 252-268, March, 1995. | |||
| BibTex | x | ||
| @article{ 10.1109/71.372775, author = {Mu-Cheng Wang and Howard Jay Siegel and Mark A. Nichols and Seth Abraham}, title = {Using a Multipath Network for Reducing the Effects of Hot Spots}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {6}, number = {3}, issn = {1045-9219}, year = {1995}, pages = {252-268}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.372775}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Parallel and Distributed Systems TI - Using a Multipath Network for Reducing the Effects of Hot Spots IS - 3 SN - 1045-9219 SP252 EP268 EPD - 252-268 A1 - Mu-Cheng Wang, A1 - Howard Jay Siegel, A1 - Mark A. Nichols, A1 - Seth Abraham, PY - 1995 VL - 6 JA - IEEE Transactions on Parallel and Distributed Systems ER - | |||
[1] S. Abraham and K. Padmanabhan,“Performance of the direct binary$n$-cube network for multiprocessors,”IEEE Trans. Comput., vol. 38, pp. 1000–1011, July 1989.
[2] G.B. Adams,D.P. Agarwal, and H.J. Siegel,"Fault-Tolerant Multistage Interconnection Networks," Computer, pp. 14-27, June 1987.
[3] G. B. Adams, III, and H. J. Siegel,“The extra stage cube: A fault-tolerant interconnection network for supersystems,”IEEE Trans. Comput., vol. C-31, pp. 443–454, May 1982.
[4] ——,“Modifications to improve the fault tolerance of the extra stage cube interconnection network,”inProc. 1984 Int. Conf. Parallel Processing, Aug. 1984, pp. 169–173.
[5] K. E. Batcher,“The flip network in STARAN,”inProc. 1976 Int. Conf. Parallel Processing, Aug. 1976, pp. 65–71.
[6] BBN Advanced Computers, Inc.,Inside the GP1000. Cambridge, MA: BBN Advanced Computers, Inc., 1990.
[7] C. Y. Chin and K. Hwang,“Packet switching networks for multiprocessors and data flow computers,”IEEE Trans. Comput., vol. C-33, pp. 991–1003, Nov. 1984.
[8] W. Crowther, J. Goodhue, R. Thomas, W. Milliken, and T. Blackadar,“Performance measurements on a 128-node butterfly parallel processor,”inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 531–540.
[9] D. M. Dias and J. R. Jump,“Analysis and simulation of buffered delta networks,”IEEE Trans. Comput., vol. C-30, pp. 273–282, Apr. 1981.
[10] A. Gottlieb, R. Grishman, C. P. Kruskal, K. P. McAuliffe, L. Rudolph, and M. Snir,“The NYU Ultracomputer designing an MIMD shared-memory parallel computer,”IEEE Trans. Comput., vol. C-32, pp. 175–189, Feb. 1983.
[11] M. J. Karol, M. G. Hluchyj, and S. P. Morgan,“Input vs. output queueing on a space-division packet switch,”inIEEE Global Telecommun. Conf., Dec. 1986, pp. 659–665.
[12] B.-C. Kang, G. Lee, and R. Kain,“Performance of multistage combining networks,”inProc. 1991 Int. Conf. Parallel Processing, Aug. 1991, pp. 550–557.
[13] J. S. Kowalik,Parallel MIMD Computation: The HEP Supercomputer and Its Applications. Cambridge, MA: The MIT Press, 1985.
[14] C. P. Kruskal and M. Snir,“The performance of multistage interconnection networks for multiprocessors,”IEEE Trans. Comput., vol. C-32, pp. 1091–1098, Dec. 1983.
[15] M. Kumar and G. F. Pfister,“The onset of hot spot contention,”inProc. 1986 Int. Conf. Parallel Processing, Aug. 1986, pp. 28–34.
[16] T. Lang and L. Kurisaki, "Nonuniform Traffic Spots (NUTS) in Multistage Interconnection Networks," J. Parallel and Distributed Computing, Sept. 1990, pp. 55-67.
[17] D. H. Lawrie,“Access and alignment of data in an array processor,”IEEE Trans. Comput., vol. C-24, pp. 1145–1155, Dec. 1975.
[18] G. Lee,“A performance bound of multistage combining networks,”IEEE Trans. Comput., vol. 38, pp. 1387–1395, Oct. 1989.
[19] G. J. Lipovski and M. Malek,Parallel Computing: Theory and Comparisons. New York: Wiley, 1987.
[20] J. H. Patel,“Performance of processor-memory interconnection networks for multiprocessors,”IEEE Trans. Comput., vol. C-30, pp. 771–780, Oct. 1981.
[21] M. C. Pease, III,“The indirect binary$n$-cube microprocessor array,”IEEE Trans. Comput., vol. C-26, pp. 458–473, May 1977.
[22] G. F. Pfister, W. C. Brantley, D. A. George, S. L. Harvey, W. J. Kleinfelder, K. P. McAuliffe, E. A. Melton, V. A. Norton, and J. Weiss,“The IBM research parallel processor prototype (RP3): Introduction and architecture,”inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 764–771.
[23] G. F. Pfister and V. A. Norton,“`Hot spot' contention and combining in multistage interconnection networks,”IEEE Trans. Comput., vol. C-34, pp. 933–938, Oct. 1985.
[24] S. L. Scott and G. S. Sohi,“Using feedback to control tree saturation in multistage interconnection networks,”inProc. 16th Annu. Int.. Symp. Comput. Archit., 1989, pp. 167–176.
[25] H. J. Siegel,“The theory underlying the partitioning of permutation networks,”IEEE Trans. Comput., vol. C-29, pp. 791–801, Sept. 1980.
[26] H.J. Siegel, Interconnection Networks for Large-Scale Parallel Processing, Second Ed., McGraw-Hill, New York, 1990.
[27] H. J. Siegel, W. G. Nation, C. P. Kruskal, and L. M. Napolitano, Jr.,“Using the multistage cube network topology in parallel supercomputers,”Proc. IEEE, vol. 77, pp. 1932–1953, Dec. 1989.
[28] H. J. Siegel, W. G. Nation, and M. D. Allemang,“The organization of the PASM reconfigurable parallel processing system,”inProc. 1990 Parallel Comput. Workshop, sponsored by the Comput. Inform. Sci. Dep., Ohio State Univ., pp. 1–12, 1990.
[29] H. J. Siegel, T. Schwederski, J. T. Kuehn, and N. J. Davis IV,“An overview of the PASM parallel processing system,”inComput. Architecture, D. D. Gajski, V. M. Milutinovic, H. J. Siegel, and B. P. Furht, Eds. Washington, DC:IEEE Computer Society Press. 1987, pp. 387–407.
[30] H. Sullivan and T.R. Bashkow, "A Large Scale, Homogenous, Fully Distributed Parallel Machine," Proc. Fourth Ann. Int'l Symp. Computer Architecture, pp. 105-117, May 1977.
[31] Y. Tamir and G. L. Frazier,“High-performance multi-queue buffers for VLSI communication switches,”inProc. 15th Ann. Int. Symp. Comput. Architecture, June 1988, pp. 343–354.
[32] S. Thanawastien and V. P. Nelson,“Interference analysis of shuffle/exchange networks,”IEEE Trans. Comput., vol. C-30, pp. 545–556, Aug. 1981.
[33] N.-F. Tzeng,“Alleviating the impact of tree saturation on multistage interconnection network performance,”J. Parallel Distrib. Comput., vol. 12, pp. 107–117, June 1991.
[34] C.-L. Wu and T. Y. Feng,“On a class of multistage interconnection networks,”IEEE Trans. Comput., vol. C-29, pp. 694–702, Aug. 1980.
[35] P. C. Yew, N. F. Tzeng, and D. H. Lawrie,“Distributing hot-spot addressing in large-scale multiprocessors,”IEEE Trans. Comput., vol. C-36, pp. 388–395, Apr. 1987.
[36] K.Y. Lee and W. Hegazy, "The Extra Stage Gamma Network," Proc. 13th Int'l Symp. Computer Architecture, pp. 175-182, June 1986.
[37] H. S. Yoon, K. Y. Lee, and M. T. Liu,“Performance analysis of multibuffered packet-switching networks in multiprocessor systems,”IEEE Trans. Comput., vol. C-39, pp. 319–327, Mar. 1990.

