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Reconfigurable Buses with Shift Switching: Concepts and Applications
January 1995 (vol. 6 no. 1)
pp. 93-102

Abstract—We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of $n$ bits can be computed in $\lceil{\log(n+1)\over\log w}\rceil$ broadcasts, each over $n$ switches, assuming a global bus of width $w$. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of $n$ bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant.

Index Terms—Reconfigurable bus systems, shift switching, parallel architectures, prefix sums, parallel counters, sorting, list ranking

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Citation:
Rong Lin, Stephan Olariu, "Reconfigurable Buses with Shift Switching: Concepts and Applications," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 1, pp. 93-102, Jan. 1995, doi:10.1109/71.363407
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