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Issue No.01 - January (1995 vol.6)
pp: 93-102
ABSTRACT
<p><it>Abstract—</it>We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of $<tmath>n</tmath>$ bits can be computed in $<tmath>\lceil{\log(n+1)\over\log w}\rceil</tmath>$ broadcasts, each over $<tmath>n</tmath>$ switches, assuming a global bus of width $<tmath>w</tmath>$. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of $<tmath>n</tmath>$ bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant.</p><p><it>Index Terms—</it>Reconfigurable bus systems, shift switching, parallel architectures, prefix sums, parallel counters, sorting, list ranking</p>
CITATION
Rong Lin, Stephan Olariu, "Reconfigurable Buses with Shift Switching: Concepts and Applications", IEEE Transactions on Parallel & Distributed Systems, vol.6, no. 1, pp. 93-102, January 1995, doi:10.1109/71.363407
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