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On Multistage Interconnection Networks with Small Clock Cycles
January 1995 (vol. 6 no. 1)
pp. 86-93

Abstract—In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. Ding and Bhuyan, however, has shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this short note, we present a model for estimating the performance of multibuffered MIN's employing the approach. Using the model, the relative effectiveness of the approach is identified compared to the traditional design.

Index Terms—Big and small clock cycles, delay, multistage interconnection networks, packet switching, throughput.

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Citation:
Hee Yong Youn, Youngsong Mun, "On Multistage Interconnection Networks with Small Clock Cycles," IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 1, pp. 86-93, Jan. 1995, doi:10.1109/71.363408
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