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Interleaved Parallel Schemes
December 1994 (vol. 5 no. 12)
pp. 1329-1334

On vector supercomputers, vector register processors share a global highly interleavedmemory. In order to optimize memory throughput, a single-instruction, multiple-data(SIMD) synchronization mode may be used on vector sections. We present an interleavedparallel scheme (IPS). Using IPS ensures an equitable distribution of elements on a highly interleaved memory for a wide range of vector strides. Access to memory may beorganized in such a way that conflicts are avoided on memory and on the interconnectionnetwork.

[1] P. Budnick and D. Kuck, "The organization and use of parallel memories,"IEEE Trans. Comput., Dec. 1971.
[2] J. M. Frailong, W. Jalby, and J. Lenfant, "XOR-schemes: A flexible organization in parallel memories," inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985.
[3] D. J. Kuck and R. A. Stokes, "The Burroughs Scientific Processor (BSP),"IEEE Trans. Comput., May 1982.
[4] D. T. Harper III and J. R. Jump, "Vector access performance in parallel memories using a skewed storage scheme,"IEEE Trans. Comput., vol. C-36, no. 12, pp. 1440-1449, 1987.
[5] J. Lenfant, "A versatile mechanism to move data in an array processor,"IEEE Trans. Comput., June 1985.
[6] A. Norton and E. Melton, "A class of Boolean linear transformations for conflict-free power-of-two stride access,"Proc. Int. Conf. Parallel Processing, 1987.
[7] B. Rau, M. Schlander, and D. Yen, "The Cydra 5 stride insensitive memory system," inProc. Int. Conf. Parallel Processing, 1989.
[8] H. Tamura, Y. Shinkai, and F. Isobe, "The supercomputer FACOM VP system,"Fujitsu Sci. Tech. J., Mar. 1985.

Index Terms:
Index Termsvector processor systems; parallel machines; synchronisation; interleaved parallelschemes; vector supercomputers; vector register processors; global highly interleavedmemory; memory throughput; synchronization mode; interconnection network
A. Seznec, J. Lenfant, "Interleaved Parallel Schemes," IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 12, pp. 1329-1334, Dec. 1994, doi:10.1109/71.334907
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