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Interleaved Parallel Schemes
December 1994 (vol. 5 no. 12)
pp. 1329-1334

On vector supercomputers, vector register processors share a global highly interleavedmemory. In order to optimize memory throughput, a single-instruction, multiple-data(SIMD) synchronization mode may be used on vector sections. We present an interleavedparallel scheme (IPS). Using IPS ensures an equitable distribution of elements on a highly interleaved memory for a wide range of vector strides. Access to memory may beorganized in such a way that conflicts are avoided on memory and on the interconnectionnetwork.

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Index Terms:
Index Termsvector processor systems; parallel machines; synchronisation; interleaved parallelschemes; vector supercomputers; vector register processors; global highly interleavedmemory; memory throughput; synchronization mode; interconnection network
Citation:
A. Seznec, J. Lenfant, "Interleaved Parallel Schemes," IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 12, pp. 1329-1334, Dec. 1994, doi:10.1109/71.334907
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