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Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses
June 1994 (vol. 5 no. 6)
pp. 664-672

We study the problem of network embeddings in 2-D array architectures in which eachrow and column of processors are interconnected by a bus. These architectures areespecially attractive if optical buses are used that allow simultaneous access by multipleprocessors through either wavelength division multiplexing or message pipelining, thusovercoming the bottlenecks caused by the exclusive access of buses. In particular, wedefine S-trees to include both binary X-trees and pyramids, and present two embeddingsof X-trees into 2-D processor arrays with spanning buses. The first embedding has theproperty that all neighboring nodes in X-trees are mapped to the same bus in the targetarray, thus allowing any two neighbors in the embedded S-trees to communicate witheach other in one routing step. The disadvantage of this embedding is its relatively highexpansion cost. In contrast, the second embedding has an expansion cost approachingunity, but does not map all neighboring nodes in X-trees to the same bus. Theseembeddings allow all algorithms designed for binary trees, pyramids, as well as X-trees to be executed on the target arrays.

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Index Terms:
Index Termsnetwork routing; multiprocessor interconnection networks; parallel architectures; binaryX-trees; pyramids; processor arrays; spanning buses; network embeddings; 2-D arrayarchitectures; binary trees; embedding; routing step
Z. Guo, R.G. Melhem, "Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses," IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 6, pp. 664-672, June 1994, doi:10.1109/71.285613
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