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Issue No.12 - December (1993 vol.4)
pp: 1332-1344
ABSTRACT
<p>Introduces a class of hierarchical networks that is suitable for implementation of largemulti-computers in VLSI with wafer scale integration (VLSI/WSI) technology. Thesenetworks, which are termed dBCube, employ the hypercube topology as a basic cluster,connect many of these clusters using a de Bruijn graph, and maintain the nodeconnectivity to be the same for all nodes product graph. The size of this class of regularnetworks can be easily extended by increments of a cluster size. Local communication, tobe satisfied by the hypercube topology, allows easy embedding of existing parallelalgorithms, while the de Bruijn graph, which was chosen for JPL's 8096-nodemultiprocessor, provides the shortest distance between clusters running different parts ofan application. A scheme for obtaining WSI layout is introduced and used to estimate thenumber of tracks needed and the required area of the wafer. The exact number of tracksin the hypercube and an approximation for the de Bruijn graph are also obtained.Tradeoffs of area versus static parameters and the size of the hypercube versus that ofthe de Bruijn graph are also discussed.</p>
INDEX TERMS
Index TermsdBCube; hierarchical multiprocessor interconnection networks; area efficient layout;hierarchical networks; VLSI; hypercube topology; de Bruijn graph; node connectivity;Communication locality; compound graph; hypercube; performance evaluation; necklace;wafer scale integration; graphs; multiprocessor interconnection networks
CITATION
C. Chen, D.P. Agrawal, J.R. Burke, "dBCube: A New Class of Hierarchical Multiprocessor Interconnection Networks with Area Efficient Layout", IEEE Transactions on Parallel & Distributed Systems, vol.4, no. 12, pp. 1332-1344, December 1993, doi:10.1109/71.250115
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