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dBCube: A New Class of Hierarchical Multiprocessor Interconnection Networks with Area Efficient Layout
December 1993 (vol. 4 no. 12)
pp. 1332-1344

Introduces a class of hierarchical networks that is suitable for implementation of largemulti-computers in VLSI with wafer scale integration (VLSI/WSI) technology. Thesenetworks, which are termed dBCube, employ the hypercube topology as a basic cluster,connect many of these clusters using a de Bruijn graph, and maintain the nodeconnectivity to be the same for all nodes product graph. The size of this class of regularnetworks can be easily extended by increments of a cluster size. Local communication, tobe satisfied by the hypercube topology, allows easy embedding of existing parallelalgorithms, while the de Bruijn graph, which was chosen for JPL's 8096-nodemultiprocessor, provides the shortest distance between clusters running different parts ofan application. A scheme for obtaining WSI layout is introduced and used to estimate thenumber of tracks needed and the required area of the wafer. The exact number of tracksin the hypercube and an approximation for the de Bruijn graph are also obtained.Tradeoffs of area versus static parameters and the size of the hypercube versus that ofthe de Bruijn graph are also discussed.

[1] D. P. Agrawal, "Advanced computer architecture," Tutorial Text, Computer Society Press, 386 pp., 1986.
[2] D. P. Agrawalet al., "Evaluating the performance of multicomputer configurations,"IEEE Comput. Mag., vol. 19, pp. 23-37, May 1986.
[3] L. N. Bhuyan and D. P. Agrawal, "Generalized hypercube and hyperbus structures for a computer networks,"IEEE Trans. Comput., vol. C-33, pp. 323-333, 1984.
[4] C. Chen, D. P. Agrawal, and J. R. Burke, "A class of hierarchical networks for VLSI/WSI based multicomputers," inProc. 4th CSI/IEEE Int. Symp. VLSI Des., Jan. 1991, pp. 267-272.
[5] C. Chen, D. P. Agrawal, and J. R. Burke, "Design and WSI layout for dBCube networks," inProc. 1991 CompEuro, May 1991, pp. 363-367.
[6] W. J. Dally, "Performance analysis ofk-aryn-cube interconnection networks,"IEEE Trans. Comput., vol. C-39, pp. 775-785, June 1990.
[7] S. P. Dandamudi and D. L. Eager, "Hierarchical interconnection networks for multicomputer systems,"IEEE Trans. Comput., vol. C-39, pp. 786-797, 1990.
[8] S. P. Dandamudi and D. L. Eager, "On hierarchical hypercube multicomputer interconnection network design,"J. Parallel Distrib. Comput., vol. 12, no. 3, pp. 283-289, July 1991.
[9] H. Fredricksen, "A survey of full length nonlinear shift register cycle algorithms,"SIAM Rev., vol. 24, pp. 195-221, 1982.
[10] E. Ganesan and D. K. Pradhan, "The hyper-de Bruijn multiprocessor networks," inProc. 11th Conf. Distrib. Comput. Syst., May 1991, pp. 492-499.
[11] K. Ghose and K. R. Desai, "The design and evaluation of the hierarchical cubic network," inProc. 1990 Int. Conf. Parallel Processing, vol. I, Aug. 1990, pp. 355-362.
[12] A. Gottliebet al., "The NYU ultracomputer--Designing an MIMD shared memory parallel computer,"IEEE Trans. Comput., vol. C-32, pp. 175-189, 1983.
[13] R. L. Graham, D. E. Knuth, and O. Patashnik,Concrete Mathematics: A Foundation for Computer Science, Research Problem 7.56. Reading, MA: Addison-Wesley, 1988, p. 366.
[14] J. P. Hayes, T. N. Mudge, and Q. F. Stout, "Architecture of a hypercube supercomputer," inProc. 1986 Int. Conf. Parallel Process., Aug. 1986, pp. 653-660.
[15] W. D. Hillis,The Connection Machine. Cambridge, MA: MIT Press, 1985.
[16] K. Hwang and J. Ghosh, "Hypernet: A communication-efficient architecture for constructing massively parallel computers,"IEEE Trans. Comput., vol. C-36, pp. 1450-1466, Dec. 1987.
[17] M. Imase and M. Itoh, "Design to minimize diameter on building-block network,"IEEE Trans. Comput., vol. C-30, pp. 439-442, 1981.
[18] J. Kim and C. R. Das, "Modeling wormhole routing in a hypercube," inProc. 11th Conf. Distrib. Comput. Syst., May 1991, pp. 386-393.
[19] D. E. Knuth,The Art of Computer Programming, Vol. 1. Reading, MA: Addison-Wesley, 1973.
[20] G. Memmi and Y. Raillard, "Some new results about the (d, k) graph problem,"IEEE Trans. Comput., vol. C-31, pp. 784-791, 1982.
[21] K. Padmanabhan, "Cube structure for multiprocessors,"Commun. ACM, vol. 33, pp. 43-52, 1990.
[22] G. F. Pfisteret al., "The IBM research parallel processor prototype (RP3): Introduction and architecture," inProc. 1985 Int. Conf. Parallel Process., Aug. 1985, pp. 764-771.
[23] D. K. Pradhan, "Interconnection topologies for fault-tolerant parallel and distributed architectures," inProc. 1981 Int. Conf. Parallel Process., Aug. 1981, pp. 238-242.
[24] F. P. Preparata and J. Vuillemin, "The cube-connected cycle: A versatile network for parallel computation,"Commun. ACM, vol. 24, pp. 300-309, May 1981.
[25] A. Ranade and S. L. Johnsson, "The communication efficiency of meshes, boolean cubes, and cube connected cycles for wafer scale integration," inProc. 1987 Int. Conf. Parallel Process., Aug. 1987, pp. 479-482.
[26] R. Rowley and B. Bose, "On necklaces in shuffle-exchange and de Bruijn networks," inProc. 1990 Int. Conf. Parallel Process., vol. I, Aug. 1990, pp. 347-350.
[27] M. R. Samatham and D. K. Pradhan, "A multiprocessor network suitable for single-chip VLSI implementation," inProc. 11th Symp. Comput. Architect., June 1984, pp. 328-337.
[28] M. L. Schlumberger, "DeBruijn communication networks," Ph.D. dissertation, Stanford Univ., Stanford, 1974.
[29] C. L. Seitz, "The Cosmic Cube,"Commun. ACM, pp. 22-33, Jan. 1985.
[30] C. L Seitzet al., "The hypercube communication chip," Dep. Comput. Sci., Calif.Inst. Technol., Display File 5182:DF:85, Mar. 1985.

Index Terms:
Index TermsdBCube; hierarchical multiprocessor interconnection networks; area efficient layout;hierarchical networks; VLSI; hypercube topology; de Bruijn graph; node connectivity;Communication locality; compound graph; hypercube; performance evaluation; necklace;wafer scale integration; graphs; multiprocessor interconnection networks
C. Chen, D.P. Agrawal, J.R. Burke, "dBCube: A New Class of Hierarchical Multiprocessor Interconnection Networks with Area Efficient Layout," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 12, pp. 1332-1344, Dec. 1993, doi:10.1109/71.250115
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