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Issue No.11 - November (1993 vol.4)
pp: 1205-1216
ABSTRACT
<p>Presents a new data flow graph model for describing the real-time execution of iterativecontrol and signal processing algorithms on multiprocessor data flow architectures.Identified by the acronym ATAMM, for Algorithm to Architecture Mapping Model, themodel is important because it specifies criteria for a multiprocessor operating system toachieve predictable and reliable performance. Algorithm performance is characterized byexecution time and iteration period. For a given data flow graph representation, the modelfacilitates calculation of greatest lower bounds for these performance measures. Whensufficient processors are available, the system executes algorithms with minimumexecution time and minimum iteration period, and the number of processors required iscalculated. When only limited processors are available or when processors fail,performance is made to degrade gracefully and predictably. The user off-line is able tospecify tradeoffs between increasing execution time or increasing iteration period. The approach to achieving predictable performance is to control the injection rate of inputdata and to modify the data flow graph precedence relations so that a processor isalways available to execute an enabled graph node. An implementation of the ATAMMmodel in a four-processor architecture based on Westinghouse's VHSIC 1750A Instruction Set Processor is described.</p>
INDEX TERMS
Index Termsperformance; data flow graph; data flow architectures; processor requirements; ATAMM;Algorithm to Architecture Mapping Model; multiprocessor operating system; reliableperformance; four-processor architecture; VHSIC 1750A Instruction Set Processor;iterative control; signal processing algorithms; periodic; nonpreemptive; dynamicmultiprocessor scheduling; real-time systems; processor requirement prediction; faulttolerant computing; multiprocessing systems; operating systems (computers); real-timesystems; scheduling
CITATION
S. Som, R.R. Mielke, J.W. Stoughton, "Prediction of Performance and Processor Requirements in Real-Time Data Flow Architectures", IEEE Transactions on Parallel & Distributed Systems, vol.4, no. 11, pp. 1205-1216, November 1993, doi:10.1109/71.250100
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