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Polymorphic Processor Arrays
May 1993 (vol. 4 no. 5)
pp. 490-506

Polymorphic processor arrays (PPAs), two-dimensional mesh-connected arrays ofprocessors in which each processor is equipped with a switch able to interconnect itsfour NEWS ports, are discussed. The main features of PPA are that it models a realisticclass of parallel computers, it supports the definition of high level programming models, it supports virtual parallelism, and it supports low complexity algorithms in a number ofapplication fields. Both the PPA computation model and the PPA programming model are presented. It is shown that the PPA computation model is realistic by relating it to thedesign of the polymorphic torus (PT) chip. It is also shown that the PPA programmingmodel is scalable by demonstrating that any algorithm having O(p) complexity on a virtual PPA of size square root m* square root m, has O(k p) complexity on a PPA of size square root n* square root n, with m k n and k integers. Some application algorithms in the area of numerical analysis and graph processing are presented.

[1] J. L. Potter, Ed.,The Massively Parallel Processor. Cambridge, MA: M.I.T. Press, 1985.
[2] S. F. Reddaway, "DAP--A flexible number cruncher," inProc. LASL Workshop Vector Parallel Processors, 1978, pp. 233-234.
[3] T. Blank, "The MasPar MP-1 Architecture," inProc. 35th IEEE Comput. Soc. Int. Conf.--Spring Compcon 90, San Francisco, CA, Feb. 1990.
[4] W. D. Hillis,The Connection Machine. Cambridge, MA: MIT Press, 1985.
[5] D. W. Blevins, E. W. Davis, R. A. Heaton, and J. H. Reif, "BLITZEN: A highly integrated massively parallel machine,"J. Parallel Distributed Comput., vol. 8, no. 2, pp. 150-160, 1990.
[6] H. Freeman and G. Pieroni, Eds.,Computer Architectures for Spatially Distributed Data. Berlin, Germany: Springer-Verlag, 1985.
[7] Q. F. Stout, "Mesh connected computers with broadcasting,"IEEE Trans. Comput., pp. 826-830, 1983.
[8] V. K. P. Kumar and M. M. Eshagian, "Parallel geometric algorithms for digitized pictures on mesh of trees," inProc. 1986 Int. Conf. Parallel Processing, 1986, pp. 270-273.
[9] R. Miller, V. K. Prasanna Kumar, D. Reisis, and Q. F. Stout, "Meshes with reconfigurable buses," inProc. 5th MIT Conf. Advanced Res. VLSI(Cambridge, MA), 1988, pp. 163-178.
[10] D. B. Shu and J. G. Nash, "The gated interconnection network for dynamic programming," inConcurrent Computations, S. K. Tewsburg, B. W. Dickinson, and S. C. Schwartz, Eds. New York: Plenum, pp. 645-658.
[11] H. Li and M. Maresca, "Polymorphic-torus network,"IEEE Trans. Comput., vol. 38, no. 9, pp. 1345-1351, Sept. 1989.
[12] B. F. Wang and G. C. Chen, "Constant time algorithms for the transitive closure and some related graph problems on processor arrays with reconfigurable bus system,"IEEE Trans. Parallel Distributed Syst., vol. 1, no. 4, pp. 500-507, Oct. 1990.
[13] M. Maresca and H. Li, "Connection autonomy in SIMD computers: A VLSI implementation,"J. Parallel Distrib. Computing, vol. 7, pp. 302-320, 1989.
[14] M. Maresca and H. Li, "A VLSI implementation of polymorphic torus architecture," inProc. 1988 Euromicro Conf. Supercomput., inMicroprocessing and Microprogramming, Euromicro J., vol. 24, pp. 737-742, 1988.
[15] M. Maresca and H. Li, "Hierarchical node clustering in polymorphic processor arrays," UCB-ICSI Tech. Rep. 91-42, July 1991.
[16] M. Maresca and H. Li, "Virtual parallelism support in reconfigurable processor arrays," UCB-ICSI Tech. Rep.-91-041, July 1991.
[17] G. Boreanaz, G. Dirosa, M. Migliardi, E. Orione, P. Baglietto, M. Maresca, and A. L. Frisiani, "Simulation of parallel algorithms for SIMD massively parallel computers," inProc. 1990 ISCS Conf. (Italian Society for Computer Simulation), Rome, Italy, Dec. 1990.
[18] M. Maresca, H. Li, and M. M. C. Sheng, "Parallel computer vision on polymorphic torus architecture,"Machine Vision Appl., vol. 2, no. 4, pp. 215-230, 1989.
[19] M. Maresca, G. Carravieri, G. Cornara, and A. L. Frisiani, "Partitioned algorithms for Gaussian elimination on reconfigurable processor arrays," inProc. 1990 Euromicro Conf., inMicroprocessing and Microprogramming, vol. 30, pp. 153-158, 1990.
[20] M. Maresca, P. Baglietto, S. Bottai, and A. L. Frisiani, "Neural network emulation on polymorphic processor arrays," inProc. IFIP Workshop Silicon Architectures for Neural Nets, Nov. 1990.
[21] Y. Shiloach and U. Vishkin, "An O(log n) parallel connectivity algorithm,"J. Algorithms, vol. 3, pp. 57-67, 1982.

Index Terms:
Index Termspolymorphic processor arrays; mesh-connected arrays; PPA; parallel computers; low complexity algorithms; PPA programming model; computational complexity; multiprocessor interconnection networks; parallel architectures; parallel processing
Citation:
M. Maresca, "Polymorphic Processor Arrays," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 5, pp. 490-506, May 1993, doi:10.1109/71.224213
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