This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Comprehensive Performance Evaluation of Crossbar Networks
May 1993 (vol. 4 no. 5)
pp. 481-489

A comprehensive model for evaluating crossbar networks in which the memory bandwidth and processor acceptance probability are primary measures considered is presented. This analytical model includes all important network control policies, such as the bus arbitration and rejected request handling policies, as well as the home memory concept. Computer simulation validates the correctness of the model. It is confirmed that the home memory and dynamic bus arbitration policy improve the network performance.

[1] D. W. L. Yen, J. H. Patel, and E. S. Davidson, "Memory interference in synchronous multiprocessor systems,"IEEE Trans. Comput., vol. C-31, pp. 1116-1121, Nov. 1982.
[2] A. S. Sethi and N. Deo, "Interference in multiprocessor systems with localized memory access probabilities,"IEEE Trans. Comput., vol. C-28, pp. 157-163, Feb. 1979.
[3] D. P. Bhandarkar, "Analysis of memory interference in multiprocessors,"IEEE Trans. Comput., vol. C-24, pp. 897-908, Sept. 1975.
[4] Y-C Liu and C-J Jou, "Effective memory bandwidth and processor blocking probability in multiple-bus systems,"IEEE Trans. Comput., vol. C-36, pp. 761-764, June 1987.
[5] L. N. Bhuyan, "An analysis of processor-memory interconnection network,"IEEE Trans. Comput., vol. C-34, pp. 279-283, Mar. 1985.
[6] K. O. Siomalas and B. A. Bowen, "Performance of crossbar multiprocessor systems,"IEEE Trans. Comput., vol. C-32, pp. 689-695, July 1983.
[7] J. H. Patel, "Multiprocessor with private cache memories,"IEEE Trans. Comput., vol. C-31, pp. 297-230, Apr. 1982.
[8] Y. C. Liu and C. Wang, "Performance of crossbar multiprocessor systems,"J. Parallel Distributed Comput., vol. 7, pp. 321-334, 1989.
[9] K. Hwang and F. A. Briggs,Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1984.
[10] T. Lang, M. Valero, and I. Alegre, "Bandwidth of crossbar and multiple-bus connections for multiprocessors,"IEEE Trans. Comput., vol. C-31, pp. 1227-1234, Dec. 1982.
[11] M. A. Holliday and M. K. Vernon, "Exact performance estimates for muitiprocessor memory and bus interference,"IEEE Trans. Comput., vol. C-36, pp. 76-85, Jan. 1987.
[12] J. H. Patel, "Performance of processor-memory interconnections for multiprocessor computer system,"IEEE Trans. Comput., vol. C-28, pp. 296-304, Sept. 1981.
[13] B. R. Rau, "Interleaved memory bandwidth in a model of a multiprocessor computer system,"IEEE Trans. Comput., vol. C-28, pp. 678-681, Sept. 1979.
[14] T. N. Mudge and B. A. Makrucki, "Probabilistic analysis of a crossbar switch," inProc. 9th Int. Symp. Comput. Architecture, Austin, TX, Apr. 1982, pp. 311-319.
[15] C. H. Hoogendoorn, "A general model for memory interference in multiprocessors,"IEEE Trans. Comput., C-26, pp. 998-1005, Oct. 1977.
[16] D. L. Chang, D. J. Kuck, and D. H. Lawrie, "On the effective bandwidth of parallel memories,"IEEE Trans. Comput., vol. C-26, pp. 76-85, May 1977.

Index Terms:
Index Termsperformance evaluation; crossbar networks; memory bandwidth; processor acceptanceprobability; bus arbitration; rejected request handling; home memory concept;multiprocessing systems; multiprocessor interconnection networks; parallel architectures;performance evaluation
Citation:
H.Y. Youn, C.C.Y. Chen, "A Comprehensive Performance Evaluation of Crossbar Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 5, pp. 481-489, May 1993, doi:10.1109/71.224212
Usage of this product signifies your acceptance of the Terms of Use.