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An Optimal Implementation of Broadcasting with Selective Reduction
March 1993 (vol. 4 no. 3)
pp. 256-269

A model of parallel computation called broadcasting with selective reduction (BSR) can be viewed as a concurrent-read concurrent-write (CRCW) parallel random access machine (PRAM) with one extension. An additional type of concurrent memory access is permitted in BSR, namely the BROADCAST instruction by means of which all N processors may gain access to all M memory locations simultaneously for the purpose of writing. At each memory location, a subset of the incoming broadcast data is selected and reduced to one value finally stored in that location. For several problems, BSR algorithms are known which require fewer steps than the corresponding best-known PRAM algorithms, using the same number of processors. A circuit is introduced to implement the BSR model, and it is shown that, in size and depth, the circuit presented is of the same order as an optimal circuit implementing the PRAM. Thus, if it is reasonable to assume that CRCW PRAM instructions execute in constant time, the assumption of a constant time BROADCAST instruction is no less reasonable.

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Index Terms:
Index Termsoptimal implementation; broadcasting with selective reduction; parallel computation;concurrent-read concurrent-write; parallel random access machine; PRAM; concurrentmemory access; BROADCAST instruction; memory locations; instruction sets; parallelalgorithms; random-access storage
Citation:
L. Fava Lindon, S.G. Akl, "An Optimal Implementation of Broadcasting with Selective Reduction," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 3, pp. 256-269, March 1993, doi:10.1109/71.210809
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