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Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound
March 1993 (vol. 4 no. 3)
pp. 241-255

A scheme for global synchronization of arbitrarily large computing structures such thatclock skew between any two communicating cells is bounded above by a constant isdescribed. The scheme utilizes clock nodes that perform simple processing on clocksignals to maintain a constant skew bound irrespective of the size of the computingstructure. Among the salient features of the scheme is the interdependence betweennetwork topology, skew upper bound, and maximum clocking rate achievable. A 2-D mesh framework is used to present the concepts, introduce three network designs, and toprove some basic results. For each network the (constant) upper bound on clock skewbetween any two communicating processors, is established, and its independence ofnetwork size is shown. Simulations were carried out to verify correctness and to checkthe workability of the scheme. A 4*4 network was built and successfully tested forstability. Such issues as node design, clocking of nonplanar structures such ashypercubes, and the concept of fuse programmed clock networks are addressed.

[1] C. L. Seitz, "System timing," inIntroduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison Wesley, 1980, ch. 7.
[2] D. Wann and M. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection networks,"IEEE Trans. Comput., vol. C-32, no. 3, pp. 284-293, Mar. 1983.
[3] S-Y. Kung, "On supercomputing with systolic/wavefront arrays,"Proc. IEEE, vol. 72, no. 7, pp. 867-884, July 1984.
[4] A. L. Fisher and H. T. Kung, "Synchronizing large VLSI arrays,"IEEE Trans. Comput., vol. C-34, pp. 734-740, Aug. 1985.
[5] M. Franklin and S. Dhar, "On designing interconnection networks for multiprocessors," inProc Int. Conf. Parallel Processing, 1986, pp. 208-215.
[6] S. Y. Kung, S. C. Lo, S. N. Jean, and J. N. Hwang, "Wavefront array processors--Concept to implementation,"IEEE Comput. Mag., vol. 20, pp. 18-33, July 1987.
[7] J. P. Fishburn, "Clock skew optimization,"IEEE Trans. Comput., vol. C-39, no. 7, pp. 945-951, July 1990.
[8] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981, pp. 21-39.
[9] M. Shoji, "Elimination of process-dependent clock skew in CMOS VLSI,"IEEE J. Solid-State Circuits, vol. SC-21, no. 5, pp. 875-880, Oct. 1986.
[10] T. Hoshino,PAX Computer: High Speed Parallel Processing and Scientific Computing. Reading, MA: Addison-Wesley, 1989, ch. 8.
[11] A. El-Amawy, "Arbitrarily large clock networks with constant skew bound," U.S. Patent 5 163068, 1992.
[12] A. El-Amawy, "Branch-and-combine clocking of arbitrarily large computing networks," inProc. Int. Conf. Parallel Processing, Aug. 1991, pp. 1-409-417.
[13] A. El-Amawy, "Properties of branch-and-combine clock networks," Tech. Report #01-91C-AE, ECE Dep., Louisiana State Univ.
[14] F. M. Klaasen, "Review of physical models for MOS transistors," inProc. NATO Advanced Study Institute on Process and Device Modeling for Integrated Circuit Design, Louvain-la-Neuve, Belgium, July 1977, pp. 541-571.
[15] Almasi, G.S., and Gottlieb, A.,Highly Parallel Computing, Benjamin/Cummings, Redwood City, Calif., 1989 [survey text: parallel architectures (Connection Machine, GF11, hypercubes, shared-memory multiprocessors, Ultra, RP3, Cedar), programming difficulties, and compiler methods].

Index Terms:
Index Termsconstant skew bound; global synchronization; arbitrarily large computing structures; clock skew; communicating cells; network topology; skew upper bound; maximum clocking rate; 2-D mesh framework; stability; node design; nonplanar structures; hypercubes; clocks; hypercube networks; parallel architectures; synchronisation
Citation:
A. El-Amawy, "Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 3, pp. 241-255, March 1993, doi:10.1109/71.210808
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