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A Novel Concurrent Error Detection Scheme for FFT Networks
February 1993 (vol. 4 no. 2)
pp. 198-221

The algorithm-based fault tolerance techniques have been proposed to obtain reliableresults at very low hardware overhead. Even though 100% fault coverage can betheoretically obtained by using these techniques, the system performance, i.e., faultcoverage and throughput, can be drastically reduced due to many practical problems,e.g., round-off errors. A novel algorithm-based fault tolerance scheme is proposed forfast Fourier transform (FFT) networks. It is shown that the proposed scheme achieves100% fault coverage theoretically. An accurate measure of the fault coverage for FFTnetworks is provided by taking the round-off error into account. The proposed scheme isshown to provide concurrent error detection capability to FFT networks with lowhardware overhead, high throughput, and high fault coverage.

[1] C. Y. Chen and J. A. Abraham, "Fault tolerance systems for the computation of eigenvalues and singular values,"Proc. SPIE, vol. 696,Advanced Algorithms and Architectures for Signal Processing, pp. 222-227, 1986.
[2] Y. H. Choi and M. Malek, "A fault tolerant FFT processor,"IEEE Trans. Comput., vol. C-37, no. 5, pp. 617-621, May 1988.
[3] S. L. Garverick and E. A. Pierce, "A single wafer 16-point 16 MHz FFT processor," inProc. Custom Integrated Circuits Conf., 1983.
[4] K. H. Huang and J. A. Abraham, "Algorithm-based fault-tolerance for matrix operations,"IEEE Trans. Comput., vol. C-33, no. 6, pp. 518-529, June 1984.
[5] J. Y. Jou and J. A. Abraham, "Fault tolerant matrix arithmetic and signal processing on highly concurrent computing structures,"Proc. IEEE, vol. 74, pp. 732-741, May 1986.
[6] J. Y. Jou and J. A. Abraham, "Fault tolerant FFT networks,"IEEE Trans. Comput., vol. C-37, no. 5, pp. 548-561, May 1988.
[7] F. T. Luk, "Algorithm-based fault tolerance for parallel matrix equation solvers,"Proc. SPIE, vol. 564,Real Time Signal Processing, pp. 49-53, 1985.
[8] F. T. Luk and H. Park, "An analysis of algorithm-based fault tolerance techniques,"Proc. SPIE, vol. 696,Advanced Algorithms and Architectures for Signal Processing, pp. 222-227, 1986.
[9] F. T. Luk and H. Park, "A fault tolerance matrix triangularizations on systolic arrays,"IEEE Trans. Comput., vol. C-37, no. 11, pp. 1434-1438, Nov. 1988.
[10] V. S. S. Nair and J. A. Abraham, "General linear codes for fault tolerant matrix operations on processor arrays," inProc. Int. Symp. Fault-Tolerant Comput., Tokyo, June 1988, pp. 180-185.
[11] A. V. Oppenheim and R. W. Schafer,Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975, ch. 9.
[12] A. Papoulis,Probability, Random Variables, and Stochastic Processes. New York: McGraw-Hill, 1965.
[13] A. L. N. Reddy and P. Banerjee, "Algorithm-based fault detection for signal processing applications,"IEEE Trans. Comput., vol. C-39, no. 11, pp. 1304-1308, Nov. 1990.
[14] K. Yamashitaet al., "A wafer-scale 170 000-gate FFT processor with built-in test circuits,"IEEE J. Solid-State Circuits, vol. 23, no. 2, pp. 336-342, Apr. 1988.
[15] P.W. Wyatt and J.I. Raffel, "Restructurable VLSI -- A Demonstrated Wafer-Scale Technology,"Proc. Int'l Conf. Wafer-Scale Integration, IEEE CS Press, Los Alamitos, Calif., Order No. 1901, 1989, pp. 13-20.
[16] P. D. Welch, "A fixed-point fast Fourier transform error analysis,"IEEE Trans. Audio Electroacoust., vol. AU-17, pp. 151-157, June 1969.

Index Terms:
Index Termsconcurrent error detection scheme; FFT networks; algorithm-based fault tolerancetechniques; system performance; fault coverage; round-off errors; digital signalprocessing chips; error detection; fast Fourier transforms; fault tolerant computing;roundoff errors
D.L. Tao, C.R.P. Hartmann, "A Novel Concurrent Error Detection Scheme for FFT Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 2, pp. 198-221, Feb. 1993, doi:10.1109/71.207595
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