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A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures
February 1993 (vol. 4 no. 2)
pp. 175-187

The authors present a compile-time scheduling heuristic called dynamic level scheduling,which accounts for interprocessor communication overhead when mappingprecedence-constrained, communicating tasks onto heterogeneous processorarchitectures with limited or possibly irregular interconnection structures. This techniqueuses dynamically-changing priorities to match tasks with processors at each step, andschedules over both spatial and temporal dimensions to eliminate shared resourcecontention. This method is fast, flexible, widely targetable, and displays promisingperformance.

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Index Terms:
Index Termsspatial dimensions; compile-time scheduling heuristic; interconnection-constrainedheterogeneous processor architectures; dynamic level scheduling; communicating tasks;temporal dimensions; parallel architectures; scheduling
Citation:
G.C. Sih, E.A. Lee, "A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 2, pp. 175-187, Feb. 1993, doi:10.1109/71.207593
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