|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| G.C. Sih, E.A. Lee, "A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 2, pp. 175-187, February, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/71.207593, author = {G.C. Sih and E.A. Lee}, title = {A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {4}, number = {2}, issn = {1045-9219}, year = {1993}, pages = {175-187}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.207593}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Parallel and Distributed Systems TI - A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures IS - 2 SN - 1045-9219 SP175 EP187 EPD - 175-187 A1 - G.C. Sih, A1 - E.A. Lee, PY - 1993 KW - Index Termsspatial dimensions; compile-time scheduling heuristic; interconnection-constrainedheterogeneous processor architectures; dynamic level scheduling; communicating tasks;temporal dimensions; parallel architectures; scheduling VL - 4 JA - IEEE Transactions on Parallel and Distributed Systems ER - | |||
The authors present a compile-time scheduling heuristic called dynamic level scheduling,which accounts for interprocessor communication overhead when mappingprecedence-constrained, communicating tasks onto heterogeneous processorarchitectures with limited or possibly irregular interconnection structures. This techniqueuses dynamically-changing priorities to match tasks with processors at each step, andschedules over both spatial and temporal dimensions to eliminate shared resourcecontention. This method is fast, flexible, widely targetable, and displays promisingperformance.
[1] S. F. Nugent, "The iPSC/2 Direct-Connect communications technology," inProc. Third Conf. Hypercube Comput. Appl., Pasadena, CA, Jan. 1988, pp. 56-60.
[2] S. Borkaret al., "iWarp: An integrated solution to high-speed parallel computing," Carnegie Mellon Tech. Rep. CMU-CS-89-104, pp. 1-10, Jan. 1989.
[3] E. A. Lee and D. G. Messerschmitt, "Static scheduling of synchronous data flow programs for digital signal processing,"IEEE Trans. Comput., vol. C-36, no. 1, pp. 24-35, Jan. 1987.
[4] E.A. Lee and S. Ha, "Scheduling Strategies for Multiprocessor Real-Time DSP,"Proc. IEEE Global Telecomm. Conf. and Exhibition (Globecom), Vol. 2, 1989, pp. 1279-1283.
[5] V. Sarkar,Partitioning and Scheduling Parallel Programs for Multiprocessing, MIT Press, 1989.
[6] W. W. Chu, L. J. Holloway, M. T. Lan, and K. Efe, "Task allocation in distributed data processing,"IEEE Comput. Mag., pp. 57-69, Nov. 1980.
[7] W. W. Chu and L. M.-T. Lan, "Task allocation and precedence relations for distributed real-time systems,"IEEE Trans. Comput., vol. C-36, pp. 667-679, June 1987.
[8] S. W. Bollinger and S. F. Midkiff, "Processor and link assignment in multicomputers using simulated annealing," in1988 ICPP Proc., vol. 1, Aug. 1988, pp. 1-7.
[9] K. Efe. "Heuristic models of task assignment scheduling in distributed systems,"IEEE Comput. Mag., pp. 50-56, June 1982.
[10] H. S. Stone, "Multiprocessor scheduling with the aid of network flow algorithms,"IEEE Trans. Software Eng., vol. SE-3, no. 1, pp. 85-93, Jan, 1977.
[11] S.J. Kim and J. C. Browne. "A general approach to mapping of parallel computations upon multiprocessor architectures," in1988 ICPP Proc., vol. 3, Aug. 1988, pp. 1-8.
[12] J. C. Bier, E. E Goei, W. H. Ho, P. D. Lapsley, M. P. O'Reilly, G. C. Sih, and E. A. Lee, "Gabriel: A design environment for DSP,"IEEE Micro Mag., Oct. 1990.
[13] R. P. Bianchini, Jr. and J. P. Shen, "Interprocessor traffic scheduling algorithm for multiple-processor networks,"IEEE Trans. Comput., vol. C-36, pp. 396-409, Apr. 1987.
[14] T.C. Hu, "Parallel sequencing and assembly line problems,"Oper. Res., vol. 9, no. 6, pp. 841-848, Nov. 1961.
[15] T. L. Adam, K. M. Chandy, and J. R. Dickson, "A comparison of list schedules for parallel processing systems,"Commun. ACM, vol. 17, no. 12, pp. 685-690, Dec. 1974.
[16] W. H. Kohler, "A preliminary evaluation of the critical path method for scheduling tasks on multiprocessor systems,"IEEE Trans. Comput., pp. 1235-1238, Dec. 1975.
[17] W.H. Yu,LU Decomposition on a Multiprocessing System with Commmunication Delay, doctoral dissertation, Dept. of Electrical Eng. and Computer Sciences, Univ. of California at Berkeley, 1984.
[18] G, C. Sih and E. A. Lee, "A multiprocessor scheduling strategy," UCB/ERL Memo, M90/119, pp. 1-34, Dec. 1990.