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| D. Lenoski, J. Laudon, T. Joe, D. Nakahira, L. Stevens, A. Gupta, J. Hennessy, "The DASH Prototype: Logic Overhead and Performance," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 1, pp. 41-61, January, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/71.205652, author = {D. Lenoski and J. Laudon and T. Joe and D. Nakahira and L. Stevens and A. Gupta and J. Hennessy}, title = {The DASH Prototype: Logic Overhead and Performance}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {4}, number = {1}, issn = {1045-9219}, year = {1993}, pages = {41-61}, doi = {http://doi.ieeecomputersociety.org/10.1109/71.205652}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Parallel and Distributed Systems TI - The DASH Prototype: Logic Overhead and Performance IS - 1 SN - 1045-9219 SP41 EP61 EPD - 41-61 A1 - D. Lenoski, A1 - J. Laudon, A1 - T. Joe, A1 - D. Nakahira, A1 - L. Stevens, A1 - A. Gupta, A1 - J. Hennessy, PY - 1993 KW - Index TermsDASH project; large-scale shared-memory multiprocessors; directory-based cachecoherence; coherent caches; hardware performance monitor; reference behavior; DASHprotocol; atomic tests; buffer storage; parallel programming; performance evaluation;shared memory systems; storage management VL - 4 JA - IEEE Transactions on Parallel and Distributed Systems ER - | |||
The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. The hardware overhead of directory-based cache coherence in a 48-processor is examined. The data show that the overhead is only about 10-15%, which appears to be a small cost for the ease of programming offered by coherent caches and the potential for higher performance. The performance of the system is discussed, and the speedups obtained by a variety of parallel applications running on the prototype are shown. Using a sophisticated hardware performance monitor, the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup are characterized. The optimizations incorporated in the DASH protocol are evaluated in terms of their effectiveness on parallel applications and on atomic tests that stress the memory system.
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