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Symmetric Crossbar Arbiters for VLSI Communication Switches
January 1993 (vol. 4 no. 1)
pp. 13-27

The design and implementation of symmetric crossbar arbiters are addressed. Severalarbiter designs are compared based on simulations of a multistage interconnectionnetwork. These simulations demonstrate the influence of the switch arbitration policy onnetwork throughput, average latency, and worst-case latency. It is shown that somenatural designs result in poor system performance and/or slow implementations. Twoefficient arbiter implementations are proposed. Based on network simulations, VLSIimplementation, and circuit simulation, it is shown that these arbiters achieve nearlyoptimal system performance without becoming the critical path that limits the systemclock.

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Index Terms:
Index TermsVLSI communication switches; symmetric crossbar arbiters; multistage interconnectionnetwork; switch arbitration policy; worst-case latency; network simulations; circuitsimulation; critical path; system clock; circuit analysis computing; multiprocessorinterconnection networks; performance evaluation; VLSI
Citation:
Y. Tamir, H.C. Chi, "Symmetric Crossbar Arbiters for VLSI Communication Switches," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 1, pp. 13-27, Jan. 1993, doi:10.1109/71.205650
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