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Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy
September 1992 (vol. 3 no. 5)
pp. 632-640
The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n/sup 2/+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained.

[1] K. A. Adiga and S. R. Deshpande, "Evaluation of effectiveness of circuit based and packet based interconnection networks via Petri net models," inProc. 1987 Int. Conf. Parallel Processing, 1987, pp. 533-541.
[2] L. N. Bhuyan, Q. Yang, and D. P. Agrawal, "Performance of multiprocessor interconnection networks,"IEEE Comput. Mag., vol. 22, pp. 25-37, Feb. 1989.
[3] N. J. Davis and H. J. Siegel, "The performance analysis of partitioned circuit switched multistage interconnection networks," inProc. 12th Symp. Comput. Architecture, 1985, pp. 387-394.
[4] N. J. Davis and H. J. Siegel, "Performance studies of multiplepacket multistage cube networks and comparison to circuit switching," inProc. 1986 Int. Conf. Parallel Processing, pp. 108-114.
[5] M. Lee and C.-L. Wu, "Performance analysis of circuit switching baseline interconnection network," inProc. 11th Annu. Symp. Comput. Architecture, 1984, pp. 82-90.
[6] J. H. Patel, "Performance of processor-memory interconnections for multiprocessors,"IEEE Trans. Comput., vol. C-30 pp. 771-780, Oct. 1981.
[7] R. W. Wolff,Stochastic Modeling and the Theory of Queues. Englewood Cliffs, NJ: Prentice-Hall, 1989.

Index Terms:
Index Termsmessage size; circuit switched multistage interconnection networks; hold strategy;performance evaluation; processor-memory communications; multiprocessor systems;processor processing time; closed queuing network model; memory access;multiprocessor interconnection networks; performance evaluation; queueing theory;switching theory
S.H. Hsiao, C.Y.R. Chen, "Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy," IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 5, pp. 632-640, Sept. 1992, doi:10.1109/71.159047
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