Issue No.04 - July (1992 vol.3)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.149967
Performing reduction operations with distributed memory machines whose interconnection networks are reconfigurable is considered. The focus is on machines whose interconnection graph can be configured as any graph of maximum degree d. The best way of interconnecting the p processors as a function of p,d and some problem- and machine-dependent parameters that characterize the ratio communication/arithmetic for the reduction operation are discussed. Experiments on transputer-based networks are in good accordance with the theoretical results.
Index Termsdistributed memory machine; reconfigurable interconnection network; reductionoperations; interconnection graph; transputer-based networks; graph theory;multiprocessor interconnection networks
S. Miguet, Y. Robert, "Reduction Operations on a Distributed Memory Machine with a Reconfigurable Interconnection Network", IEEE Transactions on Parallel & Distributed Systems, vol.3, no. 4, pp. 500-505, July 1992, doi:10.1109/71.149967