Issue No.01 - January (1992 vol.3)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.113085
For given input the global trace generated by a parallel program in a shared memory multiprocessing environment may change as the memory architecture, and management policies change. A method is proposed for ensuring that a correct global trace is generated in the new environment. This method involves a new characterization of a parallel program that identifies its address change points and address affecting points. An extension of traditional process traces, called the intrinsic trace of each process, is developed. The intrinsic traces maximize the decoupling of program execution from simulation by describing the address flow graph and path expressions of each process program. At each point where an address is issued, the trace-driven simulator uses the intrinsic traces and the sequence of loads and stores before the current cycle, to determine the next address. The mapping between load and store sequences and next addresses to issue, sometimes, requires partial program reexecution. Programs that do not require partial program re-execution are called graph-traceable.
Index Termsload sequences; memory management; memory reference traces; parallel computations;trace-drive simulation; global trace; parallel program; shared memory multiprocessingenvironment; memory architecture; address change points; address affecting points;process traces; intrinsic trace; address flow graph; path expressions; store sequences;partial program reexecution; graph-traceable; parallel programming; storage management
M.A. Holliday, C.S. Ellis, "Accuracy of Memory Reference Traces of Parallel Computations in Trace-Drive Simulation", IEEE Transactions on Parallel & Distributed Systems, vol.3, no. 1, pp. 97-109, January 1992, doi:10.1109/71.113085